From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C8E0C43219 for ; Fri, 26 Apr 2019 17:19:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 283F0212F5 for ; Fri, 26 Apr 2019 17:19:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="QkEsfb8I" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 283F0212F5 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FUy+p5mDEPcWxF9C0b50Qih/e6Rdtams1A+C6MH1kvQ=; b=QkEsfb8IMK/l+tWGk1YXJrL2b WPAZPEqeR3AtTyhd5UcVlmbgHjPsTmt1e1t7SQAxgag9/or7ZpuSQqe+QMsgDzvYfyVcK0cZ0e/jx tBsznwujDABT2VFJTX1ezAOdld0TLHxnbrr9g8jOdVNsZijDPnDxikOewXuiSvobssnX5BzTa7JlU olkRwPrF5w3jkHG0coIAHpsFXLPctmyy9qBn45SmQR9ml51ZxsTlG2xQImAr1fhjYFkmLEKuE8SiS HR89N+wTT0snmDeX42K7OV5jzJT5ELbpUKH7DlX5NgniqeQQp5QZCWD+HFtv/mGXd+gEzfNi/JjLC MT2DnAKGA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hK4VI-0000Pa-A9; Fri, 26 Apr 2019 17:19:16 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hK4VE-0000PD-QL for linux-arm-kernel@lists.infradead.org; Fri, 26 Apr 2019 17:19:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84AD6A78; Fri, 26 Apr 2019 10:19:12 -0700 (PDT) Received: from [192.168.100.241] (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0E4D33F5AF; Fri, 26 Apr 2019 10:19:12 -0700 (PDT) Subject: Re: [PATCH 2/2] arm64: cacheinfo: Update cache_line_size detected from PPTT To: Shaokun Zhang , linux-arm-kernel@lists.infradead.org References: <1556242821-5080-1-git-send-email-zhangshaokun@hisilicon.com> <1556242821-5080-2-git-send-email-zhangshaokun@hisilicon.com> From: Jeremy Linton Message-ID: <8d9b4fcd-23be-be06-6afa-8cabb1e889c2@arm.com> Date: Fri, 26 Apr 2019 12:18:33 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1556242821-5080-2-git-send-email-zhangshaokun@hisilicon.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190426_101912_858314_F1B2361B X-CRM114-Status: GOOD ( 23.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , john.garry@huawei.com, Will Deacon , qiuzhenfa@hisilicon.com, guohanjun@huawei.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On 4/25/19 8:40 PM, Shaokun Zhang wrote: > cache_line_size is derived from CTR_EL0.CWG field and is called mostly > for I/O device drivers. For HiSilicon certain plantform, like the But there are core users too? Thinkgs like blk-mq, the trace ring buffer, iommu/iova, slub/slab. And a quick look seems to indicate a number of those users are going to be checking the cache line size before the cachinfo is populated (it happens fairly late via device_initcall() and a hp notifier). Is it going to be a problem if the value changes? > Kunpeng920 server SoC, cache line sizes are different between L1/2 > cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte, > but CTR_EL0.CWG is misreporting using L1 cache line size. > > We shall correct the right value which is important for I/O performance. > Let's update the cache line size if it is detected from PPTT information > when it is larger than CTR_EL0.CWG reporting. > > Cc: Catalin Marinas > Cc: Will Deacon > Reported-by: Zhenfa Qiu > Suggested-by: Catalin Marinas > Signed-off-by: Shaokun Zhang > --- > arch/arm64/include/asm/cache.h | 6 +----- > arch/arm64/kernel/cacheinfo.c | 15 +++++++++++++++ > 2 files changed, 16 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h > index 926434f413fa..f120d48b27ac 100644 > --- a/arch/arm64/include/asm/cache.h > +++ b/arch/arm64/include/asm/cache.h > @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void) > > #define __read_mostly __attribute__((__section__(".data..read_mostly"))) > > -static inline int cache_line_size(void) > -{ > - u32 cwg = cache_type_cwg(); > - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; > -} > +extern int cache_line_size(void); > > /* > * Read the effective value of CTR_EL0. > diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c > index 0bf0a835122f..0b26d53790a8 100644 > --- a/arch/arm64/kernel/cacheinfo.c > +++ b/arch/arm64/kernel/cacheinfo.c > @@ -28,6 +28,21 @@ > #define CLIDR_CTYPE(clidr, level) \ > (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) > > +int cache_line_size(void) > +{ > + u32 cwg = cache_type_cwg(); > + > + if (cwg == 0) > + return ARCH_DMA_MINALIGN; > +#ifdef CONFIG_ACPI > + /* compare cache line size detected from PPTT with CWG reporting */ > + if (coherency_max_size > (4 << cwg)) > + return coherency_max_size; > +#endif > + > + return 4 << cwg; > +} > + > static inline enum cache_type get_cache_type(int level) > { > u64 clidr; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel