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Wed, 12 Feb 2020 23:49:52 -0800 Received: from xsj-pvapsmtp01 (xsj-smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01D7niQR030444; Wed, 12 Feb 2020 23:49:45 -0800 Received: from [172.30.17.107] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1j29Fo-00009O-Nz; Wed, 12 Feb 2020 23:49:44 -0800 Subject: Re: [PATCH 0/7] microblaze: Define SMP safe operations To: Peter Zijlstra , Michal Simek Cc: linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com, arnd@arndb.de, Allison Randal , Andrew Morton , Boqun Feng , Enrico Weigelt , Greg Kroah-Hartman , Ingo Molnar , Kate Stewart , Masahiro Yamada , Mike Rapoport , Shubhrajyoti Datta , Stefan Asserhall , Thomas Gleixner , Will Deacon References: <20200212160852.GC14973@hirez.programming.kicks-ass.net> From: Michal Simek Message-ID: <8dc57ea5-0868-0707-25a7-4cd6d8a43add@xilinx.com> Date: Thu, 13 Feb 2020 08:49:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200212160852.GC14973@hirez.programming.kicks-ass.net> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(396003)(136003)(346002)(376002)(39860400002)(189003)(199004)(5660300002)(426003)(6666004)(70586007)(70206006)(31696002)(356004)(9786002)(4326008)(336012)(316002)(54906003)(81156014)(966005)(110136005)(2616005)(8936002)(8676002)(36756003)(7416002)(186003)(478600001)(81166006)(2906002)(31686004)(26005)(44832011);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB5994;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b27062db-424d-4c07-82e1-08d7b0595291 X-MS-TrafficTypeDiagnostic: DM6PR02MB5994: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-Forefront-PRVS: 031257FE13 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wvc72+sclzKFZweuQX64ve6y+A7d3XRno7PYRYl7nbU6PKoXCoZszM0B2ucS6ICFrAv5YJWzTuZbX1/5LYPSyL6iuwbcLGXQ+usw4yIfzFBDpNlzCzI9DA3EveFIMkDWzRDUChzblZE8/jsP/Hp4qfPf0tZVKD7RIO487Pw6Y7z2X2T+oDCJxoZadocNmm45advExGFBSJ4lHfN2b0z9Mwj8ctIn9utLhLD29lt2u2nnpz8k2wG77+UttE/Zd4R03FuUDQnFoG5+MbgKDNORrB4QZSp6o99SOxMeSN/28l6f6ZRg6L0dgfp6plBBfdOdRsXQ+NvCkL+YR6eVzgUzp1n12Sw79BedtVh/vY0PrqBXhusliHhbPAaoNFt3EeV0cuXADMsE7U2T1c435snFeDvDrk06q1GNa/00UxAtsPe4jjPU9vNHYVTgJDbuCyOxJIIrbYR+C94ov7JHi978bXDX280xqFc6M1wxUffF6ApX+zU8zQP8OEidf6eLiWtxC6srhIRTwG7hcLIPG1S38A== X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 07:49:57.8338 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b27062db-424d-4c07-82e1-08d7b0595291 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5994 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12. 02. 20 17:08, Peter Zijlstra wrote: > On Wed, Feb 12, 2020 at 04:42:22PM +0100, Michal Simek wrote: > >> Microblaze has 32bit exclusive load/store instructions which should be used >> instead of irq enable/disable. For more information take a look at >> https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug984-vivado-microblaze-ref.pdf >> starting from page 25. > >> arch/microblaze/include/asm/Kbuild | 1 - >> arch/microblaze/include/asm/atomic.h | 265 ++++++++++++++++++- >> arch/microblaze/include/asm/bitops.h | 189 +++++++++++++ >> arch/microblaze/include/asm/cmpxchg.h | 87 ++++++ >> arch/microblaze/include/asm/cpuinfo.h | 2 +- >> arch/microblaze/include/asm/pgtable.h | 19 +- >> arch/microblaze/include/asm/spinlock.h | 240 +++++++++++++++++ >> arch/microblaze/include/asm/spinlock_types.h | 25 ++ >> arch/microblaze/kernel/cpu/cache.c | 154 ++++++----- >> arch/microblaze/kernel/cpu/cpuinfo.c | 38 ++- >> arch/microblaze/kernel/cpu/mb.c | 207 ++++++++------- >> arch/microblaze/kernel/timer.c | 2 +- >> arch/microblaze/mm/consistent.c | 8 +- >> 13 files changed, 1040 insertions(+), 197 deletions(-) >> create mode 100644 arch/microblaze/include/asm/bitops.h >> create mode 100644 arch/microblaze/include/asm/spinlock.h >> create mode 100644 arch/microblaze/include/asm/spinlock_types.h > > I'm missing asm/barrier.h This has been sent in previous patchset. Link was in this email. > > Also that PDF (thanks for that!), seems light on memory ordering > details. > > Your comment: > > +/* > + * clear_bit doesn't imply a memory barrier > + */ > > worries me, because that would imply your ll/sc does not impose order, > but then you also don't have any explicit barriers in your locking > primitives or atomics where required. I think this is just comment which shouldn't be there. clear_bit is calling clear_bits which is using exclusive load/store instruction which should impose ordering. > > In the PDF I only find MBAR; is that what smp_mb() ends up being? yes. All barriers should end up with mbar. Stefan: Please correct me if I am wrong? Thanks, Michal