* [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 @ 2021-08-31 10:36 Taniya Das 2021-08-31 10:36 ` [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 Taniya Das 2021-09-01 1:45 ` [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 Rob Herring 0 siblings, 2 replies; 7+ messages in thread From: Taniya Das @ 2021-08-31 10:36 UTC (permalink / raw) To: Stephen Boyd, Michael Turquette Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree, robh, robh+dt, Taniya Das The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Add the LPASS clock IDs for LPASS PIL client to request for the clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- .../bindings/clock/qcom,sc7280-lpasscc.yaml | 69 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,lpass-sc7280.h | 16 +++++ 2 files changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpass-sc7280.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml new file mode 100644 index 0000000..7b62763 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7280 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7280. + + See also: + - dt-bindings/clock/qcom,lpass-sc7280.h + +properties: + compatible: + enum: + - qcom,sc7280-lpasscc + + clocks: + items: + - description: gcc_cfg_noc_lpass_clk from GCC + + clock-names: + items: + - const: iface + + '#clock-cells': + const: 1 + + reg: + minItems: 3 + items: + - description: LPASS qdsp6ss register + - description: LPASS top-cc register + - description: LPASS cc register + + reg-names: + items: + - const: qdsp6ss + - const: top_cc + - const: cc + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpass-sc7280.h> + clock-controller@3000000 { + compatible = "qcom,sc7280-lpasscc"; + reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; + reg-names = "qdsp6ss", "top_cc", "cc"; + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,lpass-sc7280.h b/include/dt-bindings/clock/qcom,lpass-sc7280.h new file mode 100644 index 0000000..a259463 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpass-sc7280.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H + +#define LPASS_Q6SS_AHBM_CLK 0 +#define LPASS_Q6SS_AHBS_CLK 1 +#define LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation. ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 2021-08-31 10:36 [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 Taniya Das @ 2021-08-31 10:36 ` Taniya Das 2021-09-01 5:38 ` Stephen Boyd 2021-09-01 1:45 ` [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 Rob Herring 1 sibling, 1 reply; 7+ messages in thread From: Taniya Das @ 2021-08-31 10:36 UTC (permalink / raw) To: Stephen Boyd, Michael Turquette Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree, robh, robh+dt, Taniya Das Add support for the lpass clock controller found on SC7280 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-sc7280.c | 216 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 225 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sc7280.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0a55967..cd7a5a1 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -394,6 +394,14 @@ config SC_LPASS_CORECC_7180 Say Y if you want to use LPASS clocks and power domains of the LPASS core clock controller. +config SC_LPASSCC_7280 + tristate "SC7280 Low Power Audio Subsystem (LPAAS) Clock Controller" + select SC_GCC_7280 + help + Support for the LPASS clock controller on SC7280 devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SC_GPUCC_7180 tristate "SC7180 Graphics Clock Controller" select SC_GCC_7180 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9825ef8..1b33f49 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o +obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c new file mode 100644 index 0000000..89f1ad6 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sc7280.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,lpass-sc7280.h> + +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" + +static struct clk_branch lpass_q6ss_ahbm_clk = { + .halt_reg = 0x1c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_q6ss_ahbm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_q6ss_ahbs_clk = { + .halt_reg = 0x20, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x20, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_q6ss_ahbs_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = { + .halt_reg = 0x0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_top_cc_lpi_q6_axim_hs_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_core_clk = { + .halt_reg = 0x20, + /* CLK_OFF would not toggle until LPASS is out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x20, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_xo_clk = { + .halt_reg = 0x38, + /* CLK_OFF would not toggle until LPASS is out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x38, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_sleep_clk = { + .halt_reg = 0x3c, + /* CLK_OFF would not toggle until LPASS is out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x3c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct regmap_config lpass_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static struct clk_regmap *lpass_cc_sc7280_clocks[] = { + [LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr, + [LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_cc_sc7280_desc = { + .config = &lpass_regmap_config, + .clks = lpass_cc_sc7280_clocks, + .num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks), +}; + +static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = { + [LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] = + &lpass_top_cc_lpi_q6_axim_hs_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = { + .config = &lpass_regmap_config, + .clks = lpass_cc_top_sc7280_clocks, + .num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks), +}; + +static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = { + [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr, + [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr, + [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = { + .config = &lpass_regmap_config, + .clks = lpass_qdsp6ss_sc7280_clocks, + .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks), +}; + +static int lpass_cc_sc7280_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc; + int ret; + + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, "iface"); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire iface clock\n"); + goto destroy_pm_clk; + } + + lpass_regmap_config.name = "qdsp6ss"; + desc = &lpass_qdsp6ss_sc7280_desc; + + ret = qcom_cc_probe_by_index(pdev, 0, desc); + if (ret) + goto destroy_pm_clk; + + lpass_regmap_config.name = "top_cc"; + desc = &lpass_cc_top_sc7280_desc; + + ret = qcom_cc_probe_by_index(pdev, 1, desc); + if (ret) + goto destroy_pm_clk; + + lpass_regmap_config.name = "cc"; + desc = &lpass_cc_sc7280_desc; + + ret = qcom_cc_probe_by_index(pdev, 2, desc); + if (ret) + goto destroy_pm_clk; + + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static const struct of_device_id lpass_cc_sc7280_match_table[] = { + { .compatible = "qcom,sc7280-lpasscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table); + +static struct platform_driver lpass_cc_sc7280_driver = { + .probe = lpass_cc_sc7280_probe, + .driver = { + .name = "sc7280-lpasscc", + .of_match_table = lpass_cc_sc7280_match_table, + }, +}; + +static int __init lpass_cc_sc7280_init(void) +{ + return platform_driver_register(&lpass_cc_sc7280_driver); +} +subsys_initcall(lpass_cc_sc7280_init); + +static void __exit lpass_cc_sc7280_exit(void) +{ + platform_driver_unregister(&lpass_cc_sc7280_driver); +} +module_exit(lpass_cc_sc7280_exit); + +MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver"); +MODULE_LICENSE("GPL v2"); -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation. ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 2021-08-31 10:36 ` [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 Taniya Das @ 2021-09-01 5:38 ` Stephen Boyd 2021-10-06 1:39 ` Taniya Das 0 siblings, 1 reply; 7+ messages in thread From: Stephen Boyd @ 2021-09-01 5:38 UTC (permalink / raw) To: Michael Turquette, Taniya Das Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree, robh, robh+dt, Taniya Das Quoting Taniya Das (2021-08-31 03:36:42) > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 0a55967..cd7a5a1 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -394,6 +394,14 @@ config SC_LPASS_CORECC_7180 > Say Y if you want to use LPASS clocks and power domains of the LPASS > core clock controller. > > +config SC_LPASSCC_7280 > + tristate "SC7280 Low Power Audio Subsystem (LPAAS) Clock Controller" > + select SC_GCC_7280 > + help > + Support for the LPASS clock controller on SC7280 devices. > + Say Y if you want to use the LPASS branch clocks of the LPASS clock > + controller to reset the LPASS subsystem. > + Can you send another patch to move SC_LPASS_CORECC_7180 under SC_GPUCC_7180? This file should be sorted on Kconfig symbol alphabetically. > config SC_GPUCC_7180 > tristate "SC7180 Graphics Clock Controller" > select SC_GCC_7180 > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 9825ef8..1b33f49 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -66,6 +66,7 @@ obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o > obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o > obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o > obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o > +obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o This one got it right, almost. LPASSCC comes before LPASS_CORECC though. > obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o > obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o > obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 2021-09-01 5:38 ` Stephen Boyd @ 2021-10-06 1:39 ` Taniya Das 0 siblings, 0 replies; 7+ messages in thread From: Taniya Das @ 2021-10-06 1:39 UTC (permalink / raw) To: Stephen Boyd, Michael Turquette Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree, robh, robh+dt Hello Stephen, Thanks for your review. On 9/1/2021 11:08 AM, Stephen Boyd wrote: > Quoting Taniya Das (2021-08-31 03:36:42) >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index 0a55967..cd7a5a1 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -394,6 +394,14 @@ config SC_LPASS_CORECC_7180 >> Say Y if you want to use LPASS clocks and power domains of the LPASS >> core clock controller. >> >> +config SC_LPASSCC_7280 >> + tristate "SC7280 Low Power Audio Subsystem (LPAAS) Clock Controller" >> + select SC_GCC_7280 >> + help >> + Support for the LPASS clock controller on SC7280 devices. >> + Say Y if you want to use the LPASS branch clocks of the LPASS clock >> + controller to reset the LPASS subsystem. >> + > > Can you send another patch to move SC_LPASS_CORECC_7180 under > SC_GPUCC_7180? This file should be sorted on Kconfig symbol > alphabetically. > Yes, will send a patch to fix. >> config SC_GPUCC_7180 >> tristate "SC7180 Graphics Clock Controller" >> select SC_GCC_7180 >> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile >> index 9825ef8..1b33f49 100644 >> --- a/drivers/clk/qcom/Makefile >> +++ b/drivers/clk/qcom/Makefile >> @@ -66,6 +66,7 @@ obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o >> obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o >> obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o >> obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o >> +obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o > > This one got it right, almost. LPASSCC comes before LPASS_CORECC though. > Next patch will fix. >> obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o >> obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o >> obj-$(CONFIG_SC_VIDEOCC_7280) += videocc-sc7280.o -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. -- ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 2021-08-31 10:36 [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 Taniya Das 2021-08-31 10:36 ` [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 Taniya Das @ 2021-09-01 1:45 ` Rob Herring 2021-10-06 1:39 ` Taniya Das 1 sibling, 1 reply; 7+ messages in thread From: Rob Herring @ 2021-09-01 1:45 UTC (permalink / raw) To: Taniya Das Cc: Stephen Boyd, Michael Turquette , Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree On Tue, Aug 31, 2021 at 04:06:41PM +0530, Taniya Das wrote: > The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic > properties that are needed in a device tree. Add the LPASS clock IDs for > LPASS PIL client to request for the clocks. > > Signed-off-by: Taniya Das <tdas@codeaurora.org> > --- > .../bindings/clock/qcom,sc7280-lpasscc.yaml | 69 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,lpass-sc7280.h | 16 +++++ > 2 files changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml > create mode 100644 include/dt-bindings/clock/qcom,lpass-sc7280.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml > new file mode 100644 > index 0000000..7b62763 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm LPASS Core Clock Controller Binding for SC7280 > + > +maintainers: > + - Taniya Das <tdas@codeaurora.org> > + > +description: | > + Qualcomm LPASS core clock control module which supports the clocks and > + power domains on SC7280. > + > + See also: > + - dt-bindings/clock/qcom,lpass-sc7280.h > + > +properties: > + compatible: > + enum: > + - qcom,sc7280-lpasscc > + > + clocks: > + items: > + - description: gcc_cfg_noc_lpass_clk from GCC > + > + clock-names: > + items: > + - const: iface > + > + '#clock-cells': > + const: 1 > + > + reg: > + minItems: 3 Don't need minItems equal to 'items' length. > + items: > + - description: LPASS qdsp6ss register > + - description: LPASS top-cc register > + - description: LPASS cc register > + > + reg-names: > + items: > + - const: qdsp6ss > + - const: top_cc > + - const: cc > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/clock/qcom,lpass-sc7280.h> > + clock-controller@3000000 { > + compatible = "qcom,sc7280-lpasscc"; > + reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; > + reg-names = "qdsp6ss", "top_cc", "cc"; > + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; > + clock-names = "iface"; > + #clock-cells = <1>; > + }; > +... > diff --git a/include/dt-bindings/clock/qcom,lpass-sc7280.h b/include/dt-bindings/clock/qcom,lpass-sc7280.h > new file mode 100644 > index 0000000..a259463 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,lpass-sc7280.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license. > +/* > + * Copyright (c) 2021, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H > +#define _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H > + > +#define LPASS_Q6SS_AHBM_CLK 0 > +#define LPASS_Q6SS_AHBS_CLK 1 > +#define LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK 2 > +#define LPASS_QDSP6SS_XO_CLK 3 > +#define LPASS_QDSP6SS_SLEEP_CLK 4 > +#define LPASS_QDSP6SS_CORE_CLK 5 > + > +#endif > -- > Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member > of the Code Aurora Forum, hosted by the Linux Foundation. > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 2021-09-01 1:45 ` [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 Rob Herring @ 2021-10-06 1:39 ` Taniya Das 0 siblings, 0 replies; 7+ messages in thread From: Taniya Das @ 2021-10-06 1:39 UTC (permalink / raw) To: Rob Herring Cc: Stephen Boyd, Michael Turquette, Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree Hello Rob, Thanks for your review. On 9/1/2021 7:15 AM, Rob Herring wrote: > On Tue, Aug 31, 2021 at 04:06:41PM +0530, Taniya Das wrote: >> The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic >> properties that are needed in a device tree. Add the LPASS clock IDs for >> LPASS PIL client to request for the clocks. >> >> Signed-off-by: Taniya Das <tdas@codeaurora.org> >> --- >> .../bindings/clock/qcom,sc7280-lpasscc.yaml | 69 ++++++++++++++++++++++ >> include/dt-bindings/clock/qcom,lpass-sc7280.h | 16 +++++ >> 2 files changed, 85 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml >> create mode 100644 include/dt-bindings/clock/qcom,lpass-sc7280.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml >> new file mode 100644 >> index 0000000..7b62763 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml >> @@ -0,0 +1,69 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm LPASS Core Clock Controller Binding for SC7280 >> + >> +maintainers: >> + - Taniya Das <tdas@codeaurora.org> >> + >> +description: | >> + Qualcomm LPASS core clock control module which supports the clocks and >> + power domains on SC7280. >> + >> + See also: >> + - dt-bindings/clock/qcom,lpass-sc7280.h >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,sc7280-lpasscc >> + >> + clocks: >> + items: >> + - description: gcc_cfg_noc_lpass_clk from GCC >> + >> + clock-names: >> + items: >> + - const: iface >> + >> + '#clock-cells': >> + const: 1 >> + >> + reg: >> + minItems: 3 > > Don't need minItems equal to 'items' length. > Next patch will fix this. >> + items: >> + - description: LPASS qdsp6ss register >> + - description: LPASS top-cc register >> + - description: LPASS cc register >> + >> + reg-names: >> + items: >> + - const: qdsp6ss >> + - const: top_cc >> + - const: cc >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> >> + #include <dt-bindings/clock/qcom,lpass-sc7280.h> >> + clock-controller@3000000 { >> + compatible = "qcom,sc7280-lpasscc"; >> + reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; >> + reg-names = "qdsp6ss", "top_cc", "cc"; >> + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; >> + clock-names = "iface"; >> + #clock-cells = <1>; >> + }; >> +... >> diff --git a/include/dt-bindings/clock/qcom,lpass-sc7280.h b/include/dt-bindings/clock/qcom,lpass-sc7280.h >> new file mode 100644 >> index 0000000..a259463 >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,lpass-sc7280.h >> @@ -0,0 +1,16 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ > > Dual license. > Yes, my bad, will fix it in the next patch. >> +/* >> + * Copyright (c) 2021, The Linux Foundation. All rights reserved. >> + */ >> + >> +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H >> +#define _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H >> + >> +#define LPASS_Q6SS_AHBM_CLK 0 >> +#define LPASS_Q6SS_AHBS_CLK 1 >> +#define LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK 2 >> +#define LPASS_QDSP6SS_XO_CLK 3 >> +#define LPASS_QDSP6SS_SLEEP_CLK 4 >> +#define LPASS_QDSP6SS_CORE_CLK 5 >> + >> +#endif >> -- >> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member >> of the Code Aurora Forum, hosted by the Linux Foundation. >> >> -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. -- ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 @ 2021-04-09 11:54 Taniya Das 2021-04-09 11:54 ` [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 Taniya Das 0 siblings, 1 reply; 7+ messages in thread From: Taniya Das @ 2021-04-09 11:54 UTC (permalink / raw) To: Stephen Boyd, Michael Turquette Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree, robh, robh+dt, Taniya Das The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Add the LPASS clock IDs for LPASS PIL client to request for the clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- .../bindings/clock/qcom,sc7280-lpasscc.yaml | 69 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,lpass-sc7280.h | 16 +++++ 2 files changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpass-sc7280.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml new file mode 100644 index 0000000..7b62763 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7280 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7280. + + See also: + - dt-bindings/clock/qcom,lpass-sc7280.h + +properties: + compatible: + enum: + - qcom,sc7280-lpasscc + + clocks: + items: + - description: gcc_cfg_noc_lpass_clk from GCC + + clock-names: + items: + - const: iface + + '#clock-cells': + const: 1 + + reg: + minItems: 3 + items: + - description: LPASS qdsp6ss register + - description: LPASS top-cc register + - description: LPASS cc register + + reg-names: + items: + - const: qdsp6ss + - const: top_cc + - const: cc + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpass-sc7280.h> + clock-controller@3000000 { + compatible = "qcom,sc7280-lpasscc"; + reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; + reg-names = "qdsp6ss", "top_cc", "cc"; + clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,lpass-sc7280.h b/include/dt-bindings/clock/qcom,lpass-sc7280.h new file mode 100644 index 0000000..a259463 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpass-sc7280.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_SC7280_H + +#define LPASS_Q6SS_AHBM_CLK 0 +#define LPASS_Q6SS_AHBS_CLK 1 +#define LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK 2 +#define LPASS_QDSP6SS_XO_CLK 3 +#define LPASS_QDSP6SS_SLEEP_CLK 4 +#define LPASS_QDSP6SS_CORE_CLK 5 + +#endif -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation. ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 2021-04-09 11:54 Taniya Das @ 2021-04-09 11:54 ` Taniya Das 0 siblings, 0 replies; 7+ messages in thread From: Taniya Das @ 2021-04-09 11:54 UTC (permalink / raw) To: Stephen Boyd, Michael Turquette Cc: Rajendra Nayak, linux-arm-msm, linux-soc, linux-clk, linux-kernel, devicetree, robh, robh+dt, Taniya Das Add support for the lpass clock controller found on SC7280 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-sc7280.c | 216 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 225 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sc7280.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 45646b8..caf986e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -361,6 +361,14 @@ config SC_LPASS_CORECC_7180 Say Y if you want to use LPASS clocks and power domains of the LPASS core clock controller. +config SC_LPASSCC_7280 + tristate "SC7280 Low Power Audio Subsystem (LPAAS) Clock Controller" + select SC_GCC_7280 + help + Support for the LPASS clock controller on SC7280 devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SC_GPUCC_7180 tristate "SC7180 Graphics Clock Controller" select SC_GCC_7180 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index c829131..6f0ab5f 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o +obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c new file mode 100644 index 0000000..89f1ad6 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sc7280.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include <linux/platform_device.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,lpass-sc7280.h> + +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" + +static struct clk_branch lpass_q6ss_ahbm_clk = { + .halt_reg = 0x1c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_q6ss_ahbm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_q6ss_ahbs_clk = { + .halt_reg = 0x20, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x20, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_q6ss_ahbs_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = { + .halt_reg = 0x0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_top_cc_lpi_q6_axim_hs_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_core_clk = { + .halt_reg = 0x20, + /* CLK_OFF would not toggle until LPASS is out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x20, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_xo_clk = { + .halt_reg = 0x38, + /* CLK_OFF would not toggle until LPASS is out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x38, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_qdsp6ss_sleep_clk = { + .halt_reg = 0x3c, + /* CLK_OFF would not toggle until LPASS is out of reset */ + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x3c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lpass_qdsp6ss_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct regmap_config lpass_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static struct clk_regmap *lpass_cc_sc7280_clocks[] = { + [LPASS_Q6SS_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr, + [LPASS_Q6SS_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_cc_sc7280_desc = { + .config = &lpass_regmap_config, + .clks = lpass_cc_sc7280_clocks, + .num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks), +}; + +static struct clk_regmap *lpass_cc_top_sc7280_clocks[] = { + [LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] = + &lpass_top_cc_lpi_q6_axim_hs_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_cc_top_sc7280_desc = { + .config = &lpass_regmap_config, + .clks = lpass_cc_top_sc7280_clocks, + .num_clks = ARRAY_SIZE(lpass_cc_top_sc7280_clocks), +}; + +static struct clk_regmap *lpass_qdsp6ss_sc7280_clocks[] = { + [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr, + [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr, + [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr, +}; + +static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = { + .config = &lpass_regmap_config, + .clks = lpass_qdsp6ss_sc7280_clocks, + .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks), +}; + +static int lpass_cc_sc7280_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc; + int ret; + + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, "iface"); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire iface clock\n"); + goto destroy_pm_clk; + } + + lpass_regmap_config.name = "qdsp6ss"; + desc = &lpass_qdsp6ss_sc7280_desc; + + ret = qcom_cc_probe_by_index(pdev, 0, desc); + if (ret) + goto destroy_pm_clk; + + lpass_regmap_config.name = "top_cc"; + desc = &lpass_cc_top_sc7280_desc; + + ret = qcom_cc_probe_by_index(pdev, 1, desc); + if (ret) + goto destroy_pm_clk; + + lpass_regmap_config.name = "cc"; + desc = &lpass_cc_sc7280_desc; + + ret = qcom_cc_probe_by_index(pdev, 2, desc); + if (ret) + goto destroy_pm_clk; + + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static const struct of_device_id lpass_cc_sc7280_match_table[] = { + { .compatible = "qcom,sc7280-lpasscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, lpass_cc_sc7280_match_table); + +static struct platform_driver lpass_cc_sc7280_driver = { + .probe = lpass_cc_sc7280_probe, + .driver = { + .name = "sc7280-lpasscc", + .of_match_table = lpass_cc_sc7280_match_table, + }, +}; + +static int __init lpass_cc_sc7280_init(void) +{ + return platform_driver_register(&lpass_cc_sc7280_driver); +} +subsys_initcall(lpass_cc_sc7280_init); + +static void __exit lpass_cc_sc7280_exit(void) +{ + platform_driver_unregister(&lpass_cc_sc7280_driver); +} +module_exit(lpass_cc_sc7280_exit); + +MODULE_DESCRIPTION("QTI LPASS_CC SC7280 Driver"); +MODULE_LICENSE("GPL v2"); -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation. ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-10-06 1:39 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-08-31 10:36 [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 Taniya Das 2021-08-31 10:36 ` [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 Taniya Das 2021-09-01 5:38 ` Stephen Boyd 2021-10-06 1:39 ` Taniya Das 2021-09-01 1:45 ` [PATCH v1 1/2] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 Rob Herring 2021-10-06 1:39 ` Taniya Das -- strict thread matches above, loose matches on Subject: below -- 2021-04-09 11:54 Taniya Das 2021-04-09 11:54 ` [PATCH v1 2/2] clk: qcom: Add lpass clock controller driver for SC7280 Taniya Das
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