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From: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
To: Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org>,
	Michal Simek
	<michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Cc: linux-fpga-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Alan Tull
	<atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>,
	Moritz Fischer
	<moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Subject: Re: [PATCH v3 2/2] fpga manager: Add Xilinx slave serial SPI driver
Date: Thu, 23 Feb 2017 10:33:13 +0100	[thread overview]
Message-ID: <8ef97075-a9a3-07cc-83df-f89860c8f15a@xilinx.com> (raw)
In-Reply-To: <20170223102852.47d5bf5d@crub>

On 23.2.2017 10:28, Anatolij Gustschin wrote:
> On Wed, 22 Feb 2017 16:04:47 +0100
> Michal Simek michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org wrote:
> ...
>>> +	/* program latency */
>>> +	usleep_range(prog_latency_1000us, prog_latency_1000us + 500);  
>>
>> Based on my colleague for spartan6 this should be 5ms and other xilinx
>> fpgas can take up to 7.5ms.
>>
>> In general, it is better to poll for INIT_B pin==High (but that takes
>> another GPIO) and wait until at least 10 ms before timeout.
> 
> checked in the ug380.pdf, it depends on the speed grade, for some
> spartan6 it can be max. 4ms, for others 5ms. It is a max. value,
> INIT_B can go high earlier, but in my hw setup INIT_B is not
> connected. Someone with a hw setup with INIT_B connected can
> add optional support for INIT_P polling.
> 
> ...
>>> +static int xilinx_spi_write_complete(struct fpga_manager *mgr,
>>> +				     struct fpga_image_info *info)
>>> +{
>>> +	struct xilinx_spi_conf *conf = mgr->priv;
>>> +	int wait;
>>> +
>>> +	if (gpiod_get_value(conf->done))
>>> +		return 0;
>>> +
>>> +	wait = info->config_complete_timeout_us / FPGA_MIN_CFG_WAIT_US;
>>> +	if (info->config_complete_timeout_us % FPGA_MIN_CFG_WAIT_US)
>>> +		wait += 1;
>>> +
>>> +	while (wait--) {
>>> +		usleep_range(FPGA_MIN_CFG_WAIT_US, FPGA_MIN_CFG_WAIT_US + 5);
>>> +
>>> +		if (gpiod_get_value(conf->done))
>>> +			return 0;
>>> +	}
>>> +  
>>
>> Based on my colleague:
>> IMHO, for step 4 it is better to do these steps to cover more possible
>> configuration DONE scenarios:
>>
>> While ((DONE==0) and (NOT TIMEOUT)) {
>>    Continue to apply CCLK cycles;
>>    Check DONE;
>>    timeout++;
>> }
>>
>> Apply at least 8 more CCLK cycles.
>>
>> The timeout should be equivalent to at least 10 ms of time.
> 
> You mead Step 8 I think, not step 4. Will see what I can change.

This was just c&p from his reply with different steps numbers. :-)

Thanks,
Michal


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      reply	other threads:[~2017-02-23  9:33 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-22 10:39 [PATCH v3 0/2] Xilinx Slave Serial FPGA Manager Anatolij Gustschin
     [not found] ` <1487759951-20711-1-git-send-email-agust-ynQEQJNshbs@public.gmane.org>
2017-02-22 10:39   ` [PATCH v3 1/2] dt: bindings: fpga: add xilinx slave-serial binding description Anatolij Gustschin
     [not found]     ` <1487759951-20711-2-git-send-email-agust-ynQEQJNshbs@public.gmane.org>
2017-02-27 22:39       ` Rob Herring
2017-02-22 10:39   ` [PATCH v3 2/2] fpga manager: Add Xilinx slave serial SPI driver Anatolij Gustschin
     [not found]     ` <1487759951-20711-3-git-send-email-agust-ynQEQJNshbs@public.gmane.org>
2017-02-22 15:04       ` Michal Simek
     [not found]         ` <e9620f07-48bd-1f83-a686-6874becbba86-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
2017-02-23  9:28           ` Anatolij Gustschin
2017-02-23  9:33             ` Michal Simek [this message]

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