diff for duplicates of <8f0d036c-b473-bf3c-8618-0fada725e7df@arm.com>
diff --git a/a/1.txt b/N1/1.txt
index 4e38d5c..7aa465a 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -4,7 +4,7 @@ On 17/02/17 17:37, Icenowy Zheng wrote:
>
> Add a DTSI file for it.
>
-> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 404 insertions(+)
@@ -17,8 +17,8 @@ On 17/02/17 17:37, Icenowy Zheng wrote:
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,404 @@
> +/*
-> + * Copyright 2017 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
-> + * Copyright 2017 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+> + * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
+> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
@@ -447,4 +447,10 @@ Thanks,
Andre
> + };
> +};
->
\ No newline at end of file
+>
+
+
+_______________________________________________
+linux-arm-kernel mailing list
+linux-arm-kernel@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
\ No newline at end of file
diff --git a/a/content_digest b/N1/content_digest
index 19fc712..f3b8edf 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -5,29 +5,26 @@
"ref\00020170217173722.6477-6-icenowy\@aosc.xyz\0"
]
[
- "ref\00020170217173722.6477-6-icenowy-ymACFijhrKM\@public.gmane.org\0"
+ "From\0Andr\303\251 Przywara <andre.przywara\@arm.com>\0"
]
[
- "From\0Andr\303\251 Przywara <andre.przywara-5wv7dgnIgG8\@public.gmane.org>\0"
-]
-[
- "Subject\0Re: [RFC PATCH 5/9] ARM: dts: sun8i: add DTSI file for R40 SoC\0"
+ "Subject\0Re: [linux-sunxi] [RFC PATCH 5/9] ARM: dts: sun8i: add DTSI file for R40 SoC\0"
]
[
"Date\0Fri, 17 Feb 2017 22:17:00 +0000\0"
]
[
- "To\0icenowy-ymACFijhrKM\@public.gmane.org",
- " Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>",
- " Chen-Yu Tsai <wens-jdAy2FN1RRM\@public.gmane.org>",
- " Kishon Vijay Abraham I <kishon-l0cyMroinI0\@public.gmane.org>",
- " Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>\0"
+ "To\0icenowy\@aosc.xyz",
+ " Maxime Ripard <maxime.ripard\@free-electrons.com>",
+ " Chen-Yu Tsai <wens\@csie.org>",
+ " Kishon Vijay Abraham I <kishon\@ti.com>",
+ " Linus Walleij <linus.walleij\@linaro.org>\0"
]
[
- "Cc\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org",
- " linux-gpio-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-clk-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw\@public.gmane.org\0"
+ "Cc\0linux-gpio\@vger.kernel.org",
+ " linux-sunxi\@googlegroups.com",
+ " linux-clk\@vger.kernel.org",
+ " linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -42,7 +39,7 @@
"> \n",
"> Add a DTSI file for it.\n",
"> \n",
- "> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM\@public.gmane.org>\n",
+ "> Signed-off-by: Icenowy Zheng <icenowy\@aosc.xyz>\n",
"> ---\n",
"> arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++++++++++++++++++++++++++++++++++++++\n",
"> 1 file changed, 404 insertions(+)\n",
@@ -55,8 +52,8 @@
"> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi\n",
"> \@\@ -0,0 +1,404 \@\@\n",
"> +/*\n",
- "> + * Copyright 2017 Chen-Yu Tsai <wens-jdAy2FN1RRM\@public.gmane.org>\n",
- "> + * Copyright 2017 Icenowy Zheng <icenowy-ymACFijhrKM\@public.gmane.org>\n",
+ "> + * Copyright 2017 Chen-Yu Tsai <wens\@csie.org>\n",
+ "> + * Copyright 2017 Icenowy Zheng <icenowy\@aosc.xyz>\n",
"> + *\n",
"> + * This file is dual-licensed: you can use it either under the terms\n",
"> + * of the GPL or the X11 license, at your option. Note that this dual\n",
@@ -485,7 +482,13 @@
"Andre\n",
"> +\t};\n",
"> +};\n",
- ">"
+ "> \n",
+ "\n",
+ "\n",
+ "_______________________________________________\n",
+ "linux-arm-kernel mailing list\n",
+ "linux-arm-kernel\@lists.infradead.org\n",
+ "http://lists.infradead.org/mailman/listinfo/linux-arm-kernel"
]
-278539d271adfd3a392d2dfd2b0df8e10ebe92bc241d3fe765348aa639eedca2
+703366733bdf04f0a08eb377d05f9acec284a2dc389170206c7f96b7fee17494
diff --git a/a/1.txt b/N2/1.txt
index 4e38d5c..26b6935 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -4,7 +4,7 @@ On 17/02/17 17:37, Icenowy Zheng wrote:
>
> Add a DTSI file for it.
>
-> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 404 insertions(+)
@@ -17,8 +17,8 @@ On 17/02/17 17:37, Icenowy Zheng wrote:
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -0,0 +1,404 @@
> +/*
-> + * Copyright 2017 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
-> + * Copyright 2017 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+> + * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
+> + * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
@@ -97,25 +97,25 @@ On 17/02/17 17:37, Icenowy Zheng wrote:
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
-> + cpu@0 {
+> + cpu at 0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
-> + cpu@1 {
+> + cpu at 1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
-> + cpu@2 {
+> + cpu at 2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
-> + cpu@3 {
+> + cpu at 3 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <3>;
@@ -127,13 +127,13 @@ On 17/02/17 17:37, Icenowy Zheng wrote:
> + reg = <0x40000000 0x80000000>;
> + };
> +
-> + soc@01c00000 {
+> + soc at 01c00000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
-> + nmi_intc: interrupt-controller@01c00030 {
+> + nmi_intc: interrupt-controller at 01c00030 {
> + compatible = "allwinner,sun7i-a20-sc-nmi";
> + interrupt-controller;
> + #interrupt-cells = <2>;
@@ -141,7 +141,7 @@ On 17/02/17 17:37, Icenowy Zheng wrote:
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
-> + mmc0: mmc@1c0f000 {
+> + mmc0: mmc at 1c0f000 {
> + compatible = "allwinner,sun50i-a64-mmc";
Can you please add a SoC specific compatible in the first place?
@@ -163,7 +163,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + mmc1: mmc@1c10000 {
+> + mmc1: mmc at 1c10000 {
> + compatible = "allwinner,sun50i-a64-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
@@ -177,7 +177,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + mmc2: mmc@1c11000 {
+> + mmc2: mmc at 1c11000 {
> + compatible = "allwinner,sun50i-a64-emmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
@@ -191,7 +191,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + mmc3: mmc@1c12000 {
+> + mmc3: mmc at 1c12000 {
> + compatible = "allwinner,sun50i-a64-mmc";
> + reg = <0x01c12000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
@@ -205,7 +205,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + ccu: clock@01c20000 {
+> + ccu: clock at 01c20000 {
> + compatible = "allwinner,sun8i-r40-ccu";
> + reg = <0x01c20000 0x400>;
> + clocks = <&osc24M>, <&osc32k>;
@@ -214,7 +214,7 @@ Same for the others MMC controllers.
> + #reset-cells = <1>;
> + };
> +
-> + pio: pinctrl@01c20800 {
+> + pio: pinctrl at 01c20800 {
> + compatible = "allwinner,sun8i-r40-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -225,12 +225,12 @@ Same for the others MMC controllers.
> + #interrupt-cells = <3>;
> + #gpio-cells = <3>;
> +
-> + i2c0_pins: twi0@0 {
+> + i2c0_pins: twi0 at 0 {
> + pins = "PB0", "PB1";
> + function = "i2c0";
> + };
> +
-> + mmc0_pins: mmc0@0 {
+> + mmc0_pins: mmc0 at 0 {
> + pins = "PF0", "PF1", "PF2",
> + "PF3", "PF4", "PF5";
> + function = "mmc0";
@@ -238,7 +238,7 @@ Same for the others MMC controllers.
> + bias-pull-up;
> + };
> +
-> + mmc1_pins: mmc1@0 {
+> + mmc1_pins: mmc1 at 0 {
> + pins = "PG0", "PG1", "PG2",
> + "PG3", "PG4", "PG5";
> + function = "mmc1";
@@ -246,7 +246,7 @@ Same for the others MMC controllers.
> + bias-pull-up;
> + };
> +
-> + mmc2_pins: mmc2@0 {
+> + mmc2_pins: mmc2 at 0 {
> + pins = "PC5", "PC6", "PC7", "PC8", "PC9",
> + "PC10", "PC11", "PC12", "PC13", "PC14",
> + "PC15", "PC24";
@@ -255,13 +255,13 @@ Same for the others MMC controllers.
> + bias-pull-up;
> + };
> +
-> + uart0_pins_0: uart0@0 {
+> + uart0_pins_0: uart0 at 0 {
> + pins = "PB22", "PB23";
> + function = "uart0";
> + };
> + };
> +
-> + uart0: serial@01c28000 {
+> + uart0: serial at 01c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
@@ -272,7 +272,7 @@ Same for the others MMC controllers.
> + status = "disabled";
> + };
> +
-> + uart1: serial@01c28400 {
+> + uart1: serial at 01c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -283,7 +283,7 @@ Same for the others MMC controllers.
> + status = "disabled";
> + };
> +
-> + uart2: serial@01c28800 {
+> + uart2: serial at 01c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -294,7 +294,7 @@ Same for the others MMC controllers.
> + status = "disabled";
> + };
> +
-> + uart3: serial@01c28c00 {
+> + uart3: serial at 01c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
@@ -305,7 +305,7 @@ Same for the others MMC controllers.
> + status = "disabled";
> + };
> +
-> + uart4: serial@01c29000 {
+> + uart4: serial at 01c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
@@ -316,7 +316,7 @@ Same for the others MMC controllers.
> + status = "disabled";
> + };
> +
-> + uart5: serial@01c29400 {
+> + uart5: serial at 01c29400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29400 0x400>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -327,7 +327,7 @@ Same for the others MMC controllers.
> + status = "disabled";
> + };
> +
-> + uart6: serial@01c29800 {
+> + uart6: serial at 01c29800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29800 0x400>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -338,7 +338,7 @@ Same for the others MMC controllers.
> + status = "disabled";
> + };
> +
-> + uart7: serial@01c29c00 {
+> + uart7: serial at 01c29c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29c00 0x400>;
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -349,7 +349,7 @@ Same for the others MMC controllers.
> + status = "disabled";
> + };
> +
-> + i2c0: i2c@01c2ac00 {
+> + i2c0: i2c at 01c2ac00 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -362,7 +362,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + i2c1: i2c@01c2b000 {
+> + i2c1: i2c at 01c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
@@ -373,7 +373,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + i2c2: i2c@01c2b400 {
+> + i2c2: i2c at 01c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
@@ -384,7 +384,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + i2c3: i2c@01c2b800 {
+> + i2c3: i2c at 01c2b800 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b800 0x400>;
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
@@ -395,7 +395,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + i2c4: i2c@01c2c000 {
+> + i2c4: i2c at 01c2c000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2c000 0x400>;
> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
@@ -406,7 +406,7 @@ Same for the others MMC controllers.
> + #size-cells = <0>;
> + };
> +
-> + gic: interrupt-controller@01c81000 {
+> + gic: interrupt-controller at 01c81000 {
> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
I wonder if we should use the opportunity to change this to something
diff --git a/a/content_digest b/N2/content_digest
index 19fc712..73ba058 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -5,29 +5,16 @@
"ref\00020170217173722.6477-6-icenowy\@aosc.xyz\0"
]
[
- "ref\00020170217173722.6477-6-icenowy-ymACFijhrKM\@public.gmane.org\0"
+ "From\0andre.przywara\@arm.com (Andr\303\251 Przywara)\0"
]
[
- "From\0Andr\303\251 Przywara <andre.przywara-5wv7dgnIgG8\@public.gmane.org>\0"
-]
-[
- "Subject\0Re: [RFC PATCH 5/9] ARM: dts: sun8i: add DTSI file for R40 SoC\0"
+ "Subject\0[linux-sunxi] [RFC PATCH 5/9] ARM: dts: sun8i: add DTSI file for R40 SoC\0"
]
[
"Date\0Fri, 17 Feb 2017 22:17:00 +0000\0"
]
[
- "To\0icenowy-ymACFijhrKM\@public.gmane.org",
- " Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>",
- " Chen-Yu Tsai <wens-jdAy2FN1RRM\@public.gmane.org>",
- " Kishon Vijay Abraham I <kishon-l0cyMroinI0\@public.gmane.org>",
- " Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>\0"
-]
-[
- "Cc\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org",
- " linux-gpio-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-clk-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw\@public.gmane.org\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -42,7 +29,7 @@
"> \n",
"> Add a DTSI file for it.\n",
"> \n",
- "> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM\@public.gmane.org>\n",
+ "> Signed-off-by: Icenowy Zheng <icenowy\@aosc.xyz>\n",
"> ---\n",
"> arch/arm/boot/dts/sun8i-r40.dtsi | 404 +++++++++++++++++++++++++++++++++++++++\n",
"> 1 file changed, 404 insertions(+)\n",
@@ -55,8 +42,8 @@
"> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi\n",
"> \@\@ -0,0 +1,404 \@\@\n",
"> +/*\n",
- "> + * Copyright 2017 Chen-Yu Tsai <wens-jdAy2FN1RRM\@public.gmane.org>\n",
- "> + * Copyright 2017 Icenowy Zheng <icenowy-ymACFijhrKM\@public.gmane.org>\n",
+ "> + * Copyright 2017 Chen-Yu Tsai <wens\@csie.org>\n",
+ "> + * Copyright 2017 Icenowy Zheng <icenowy\@aosc.xyz>\n",
"> + *\n",
"> + * This file is dual-licensed: you can use it either under the terms\n",
"> + * of the GPL or the X11 license, at your option. Note that this dual\n",
@@ -135,25 +122,25 @@
"> +\t\t#address-cells = <1>;\n",
"> +\t\t#size-cells = <0>;\n",
"> +\n",
- "> +\t\tcpu\@0 {\n",
+ "> +\t\tcpu at 0 {\n",
"> +\t\t\tcompatible = \"arm,cortex-a7\";\n",
"> +\t\t\tdevice_type = \"cpu\";\n",
"> +\t\t\treg = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tcpu\@1 {\n",
+ "> +\t\tcpu at 1 {\n",
"> +\t\t\tcompatible = \"arm,cortex-a7\";\n",
"> +\t\t\tdevice_type = \"cpu\";\n",
"> +\t\t\treg = <1>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tcpu\@2 {\n",
+ "> +\t\tcpu at 2 {\n",
"> +\t\t\tcompatible = \"arm,cortex-a7\";\n",
"> +\t\t\tdevice_type = \"cpu\";\n",
"> +\t\t\treg = <2>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tcpu\@3 {\n",
+ "> +\t\tcpu at 3 {\n",
"> +\t\t\tcompatible = \"arm,cortex-a7\";\n",
"> +\t\t\tdevice_type = \"cpu\";\n",
"> +\t\t\treg = <3>;\n",
@@ -165,13 +152,13 @@
"> +\t\treg = <0x40000000 0x80000000>;\n",
"> +\t};\n",
"> +\n",
- "> +\tsoc\@01c00000 {\n",
+ "> +\tsoc at 01c00000 {\n",
"> +\t\tcompatible = \"simple-bus\";\n",
"> +\t\t#address-cells = <1>;\n",
"> +\t\t#size-cells = <1>;\n",
"> +\t\tranges;\n",
"> +\n",
- "> +\t\tnmi_intc: interrupt-controller\@01c00030 {\n",
+ "> +\t\tnmi_intc: interrupt-controller at 01c00030 {\n",
"> +\t\t\tcompatible = \"allwinner,sun7i-a20-sc-nmi\";\n",
"> +\t\t\tinterrupt-controller;\n",
"> +\t\t\t#interrupt-cells = <2>;\n",
@@ -179,7 +166,7 @@
"> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tmmc0: mmc\@1c0f000 {\n",
+ "> +\t\tmmc0: mmc at 1c0f000 {\n",
"> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\";\n",
"\n",
"Can you please add a SoC specific compatible in the first place?\n",
@@ -201,7 +188,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tmmc1: mmc\@1c10000 {\n",
+ "> +\t\tmmc1: mmc at 1c10000 {\n",
"> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\";\n",
"> +\t\t\treg = <0x01c10000 0x1000>;\n",
"> +\t\t\tclocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;\n",
@@ -215,7 +202,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tmmc2: mmc\@1c11000 {\n",
+ "> +\t\tmmc2: mmc at 1c11000 {\n",
"> +\t\t\tcompatible = \"allwinner,sun50i-a64-emmc\";\n",
"> +\t\t\treg = <0x01c11000 0x1000>;\n",
"> +\t\t\tclocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;\n",
@@ -229,7 +216,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tmmc3: mmc\@1c12000 {\n",
+ "> +\t\tmmc3: mmc at 1c12000 {\n",
"> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\";\n",
"> +\t\t\treg = <0x01c12000 0x1000>;\n",
"> +\t\t\tclocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;\n",
@@ -243,7 +230,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tccu: clock\@01c20000 {\n",
+ "> +\t\tccu: clock at 01c20000 {\n",
"> +\t\t\tcompatible = \"allwinner,sun8i-r40-ccu\";\n",
"> +\t\t\treg = <0x01c20000 0x400>;\n",
"> +\t\t\tclocks = <&osc24M>, <&osc32k>;\n",
@@ -252,7 +239,7 @@
"> +\t\t\t#reset-cells = <1>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tpio: pinctrl\@01c20800 {\n",
+ "> +\t\tpio: pinctrl at 01c20800 {\n",
"> +\t\t\tcompatible = \"allwinner,sun8i-r40-pinctrl\";\n",
"> +\t\t\treg = <0x01c20800 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -263,12 +250,12 @@
"> +\t\t\t#interrupt-cells = <3>;\n",
"> +\t\t\t#gpio-cells = <3>;\n",
"> +\n",
- "> +\t\t\ti2c0_pins: twi0\@0 {\n",
+ "> +\t\t\ti2c0_pins: twi0 at 0 {\n",
"> +\t\t\t\tpins = \"PB0\", \"PB1\";\n",
"> +\t\t\t\tfunction = \"i2c0\";\n",
"> +\t\t\t};\n",
"> +\n",
- "> +\t\t\tmmc0_pins: mmc0\@0 {\n",
+ "> +\t\t\tmmc0_pins: mmc0 at 0 {\n",
"> +\t\t\t\tpins = \"PF0\", \"PF1\", \"PF2\",\n",
"> +\t\t\t\t \"PF3\", \"PF4\", \"PF5\";\n",
"> +\t\t\t\tfunction = \"mmc0\";\n",
@@ -276,7 +263,7 @@
"> +\t\t\t\tbias-pull-up;\n",
"> +\t\t\t};\n",
"> +\n",
- "> +\t\t\tmmc1_pins: mmc1\@0 {\n",
+ "> +\t\t\tmmc1_pins: mmc1 at 0 {\n",
"> +\t\t\t\tpins = \"PG0\", \"PG1\", \"PG2\",\n",
"> +\t\t\t\t \"PG3\", \"PG4\", \"PG5\";\n",
"> +\t\t\t\tfunction = \"mmc1\";\n",
@@ -284,7 +271,7 @@
"> +\t\t\t\tbias-pull-up;\n",
"> +\t\t\t};\n",
"> +\n",
- "> +\t\t\tmmc2_pins: mmc2\@0 {\n",
+ "> +\t\t\tmmc2_pins: mmc2 at 0 {\n",
"> +\t\t\t\tpins = \"PC5\", \"PC6\", \"PC7\", \"PC8\", \"PC9\",\n",
"> +\t\t\t\t \"PC10\", \"PC11\", \"PC12\", \"PC13\", \"PC14\",\n",
"> +\t\t\t\t \"PC15\", \"PC24\";\n",
@@ -293,13 +280,13 @@
"> +\t\t\t\tbias-pull-up;\n",
"> +\t\t\t};\n",
"> +\n",
- "> +\t\t\tuart0_pins_0: uart0\@0 {\n",
+ "> +\t\t\tuart0_pins_0: uart0 at 0 {\n",
"> +\t\t\t\tpins = \"PB22\", \"PB23\";\n",
"> +\t\t\t\tfunction = \"uart0\";\n",
"> +\t\t\t};\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tuart0: serial\@01c28000 {\n",
+ "> +\t\tuart0: serial at 01c28000 {\n",
"> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"> +\t\t\treg = <0x01c28000 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -310,7 +297,7 @@
"> +\t\t\tstatus = \"disabled\";\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tuart1: serial\@01c28400 {\n",
+ "> +\t\tuart1: serial at 01c28400 {\n",
"> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"> +\t\t\treg = <0x01c28400 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -321,7 +308,7 @@
"> +\t\t\tstatus = \"disabled\";\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tuart2: serial\@01c28800 {\n",
+ "> +\t\tuart2: serial at 01c28800 {\n",
"> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"> +\t\t\treg = <0x01c28800 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -332,7 +319,7 @@
"> +\t\t\tstatus = \"disabled\";\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tuart3: serial\@01c28c00 {\n",
+ "> +\t\tuart3: serial at 01c28c00 {\n",
"> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"> +\t\t\treg = <0x01c28c00 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -343,7 +330,7 @@
"> +\t\t\tstatus = \"disabled\";\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tuart4: serial\@01c29000 {\n",
+ "> +\t\tuart4: serial at 01c29000 {\n",
"> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"> +\t\t\treg = <0x01c29000 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -354,7 +341,7 @@
"> +\t\t\tstatus = \"disabled\";\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tuart5: serial\@01c29400 {\n",
+ "> +\t\tuart5: serial at 01c29400 {\n",
"> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"> +\t\t\treg = <0x01c29400 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -365,7 +352,7 @@
"> +\t\t\tstatus = \"disabled\";\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tuart6: serial\@01c29800 {\n",
+ "> +\t\tuart6: serial at 01c29800 {\n",
"> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"> +\t\t\treg = <0x01c29800 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -376,7 +363,7 @@
"> +\t\t\tstatus = \"disabled\";\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tuart7: serial\@01c29c00 {\n",
+ "> +\t\tuart7: serial at 01c29c00 {\n",
"> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"> +\t\t\treg = <0x01c29c00 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -387,7 +374,7 @@
"> +\t\t\tstatus = \"disabled\";\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\ti2c0: i2c\@01c2ac00 {\n",
+ "> +\t\ti2c0: i2c at 01c2ac00 {\n",
"> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n",
"> +\t\t\treg = <0x01c2ac00 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -400,7 +387,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\ti2c1: i2c\@01c2b000 {\n",
+ "> +\t\ti2c1: i2c at 01c2b000 {\n",
"> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n",
"> +\t\t\treg = <0x01c2b000 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -411,7 +398,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\ti2c2: i2c\@01c2b400 {\n",
+ "> +\t\ti2c2: i2c at 01c2b400 {\n",
"> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n",
"> +\t\t\treg = <0x01c2b400 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -422,7 +409,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\ti2c3: i2c\@01c2b800 {\n",
+ "> +\t\ti2c3: i2c at 01c2b800 {\n",
"> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n",
"> +\t\t\treg = <0x01c2b800 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -433,7 +420,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\ti2c4: i2c\@01c2c000 {\n",
+ "> +\t\ti2c4: i2c at 01c2c000 {\n",
"> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n",
"> +\t\t\treg = <0x01c2c000 0x400>;\n",
"> +\t\t\tinterrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -444,7 +431,7 @@
"> +\t\t\t#size-cells = <0>;\n",
"> +\t\t};\n",
"> +\n",
- "> +\t\tgic: interrupt-controller\@01c81000 {\n",
+ "> +\t\tgic: interrupt-controller at 01c81000 {\n",
"> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n",
"\n",
"I wonder if we should use the opportunity to change this to something\n",
@@ -488,4 +475,4 @@
">"
]
-278539d271adfd3a392d2dfd2b0df8e10ebe92bc241d3fe765348aa639eedca2
+484dd87f940f2b606ef808bbac9b3539db42558e01e37cfc357d2073e9cf1263
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