From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2354C433E2 for ; Wed, 22 Jul 2020 10:31:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C20CC20729 for ; Wed, 22 Jul 2020 10:31:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=shipmail.org header.i=@shipmail.org header.b="hVBS9izU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726821AbgGVKbg (ORCPT ); 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Wed, 22 Jul 2020 12:31:26 +0200 (CEST) Received: from [192.168.0.100] (h-205-35.A357.priv.bahnhof.se [155.4.205.35]) by mail1.shipmail.org (Postfix) with ESMTPSA id 7E2F3362551; Wed, 22 Jul 2020 12:31:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=shipmail.org; s=mail; t=1595413887; bh=IdgBtUFYB5h3M894fLyGzRGoV7q+2iBbuY3az/yTSL4=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=hVBS9izUpG83NeG87m7+xU3OHQ4U+Wjnh7+3vi2hm9cmFIevDBo+SKzqLY3d6FUNx PCrnVe16MF3td3ncQavKnAgFgKC6DSPBn0crb2FuBw0xFKvaHgNkxnGVHyo/HuWbWP xiy3+ufveb/XDPRihBAsaKMD6mHJ4HNLcpsKNOdk= Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea To: Daniel Vetter Cc: Dave Airlie , =?UTF-8?Q?Christian_K=c3=b6nig?= , Daniel Stone , linux-rdma , Intel Graphics Development , Maarten Lankhorst , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Steve Pronovost , amd-gfx mailing list , Jason Ekstrand , Jesse Natalie , Daniel Vetter , Thomas Hellstrom , Mika Kuoppala , Felix Kuehling , Linux Media Mailing List References: <20200707201229.472834-4-daniel.vetter@ffwll.ch> <20200709123339.547390-1-daniel.vetter@ffwll.ch> <93b673b7-bb48-96eb-dc2c-bd4f9304000e@shipmail.org> <20200721074157.GB3278063@phenom.ffwll.local> <3603bb71-318b-eb53-0532-9daab62dce86@amd.com> <57a5eb9d-b74f-8ce4-7199-94e911d9b68b@shipmail.org> <805c49b7-f0b3-45dc-5fe3-b352f0971527@shipmail.org> <92393d26-d863-aac6-6d27-53cad6854e13@shipmail.org> From: =?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?= Message-ID: <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> Date: Wed, 22 Jul 2020 12:31:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org On 2020-07-22 11:45, Daniel Vetter wrote: > On Wed, Jul 22, 2020 at 10:05 AM Thomas Hellström (Intel) > wrote: >> >> On 2020-07-22 09:11, Daniel Vetter wrote: >>> On Wed, Jul 22, 2020 at 8:45 AM Thomas Hellström (Intel) >>> wrote: >>>> On 2020-07-22 00:45, Dave Airlie wrote: >>>>> On Tue, 21 Jul 2020 at 18:47, Thomas Hellström (Intel) >>>>> wrote: >>>>>> On 7/21/20 9:45 AM, Christian König wrote: >>>>>>> Am 21.07.20 um 09:41 schrieb Daniel Vetter: >>>>>>>> On Mon, Jul 20, 2020 at 01:15:17PM +0200, Thomas Hellström (Intel) >>>>>>>> wrote: >>>>>>>>> Hi, >>>>>>>>> >>>>>>>>> On 7/9/20 2:33 PM, Daniel Vetter wrote: >>>>>>>>>> Comes up every few years, gets somewhat tedious to discuss, let's >>>>>>>>>> write this down once and for all. >>>>>>>>>> >>>>>>>>>> What I'm not sure about is whether the text should be more explicit in >>>>>>>>>> flat out mandating the amdkfd eviction fences for long running compute >>>>>>>>>> workloads or workloads where userspace fencing is allowed. >>>>>>>>> Although (in my humble opinion) it might be possible to completely >>>>>>>>> untangle >>>>>>>>> kernel-introduced fences for resource management and dma-fences used >>>>>>>>> for >>>>>>>>> completion- and dependency tracking and lift a lot of restrictions >>>>>>>>> for the >>>>>>>>> dma-fences, including prohibiting infinite ones, I think this makes >>>>>>>>> sense >>>>>>>>> describing the current state. >>>>>>>> Yeah I think a future patch needs to type up how we want to make that >>>>>>>> happen (for some cross driver consistency) and what needs to be >>>>>>>> considered. Some of the necessary parts are already there (with like the >>>>>>>> preemption fences amdkfd has as an example), but I think some clear docs >>>>>>>> on what's required from both hw, drivers and userspace would be really >>>>>>>> good. >>>>>>> I'm currently writing that up, but probably still need a few days for >>>>>>> this. >>>>>> Great! I put down some (very) initial thoughts a couple of weeks ago >>>>>> building on eviction fences for various hardware complexity levels here: >>>>>> >>>>>> https://gitlab.freedesktop.org/thomash/docs/-/blob/master/Untangling%20dma-fence%20and%20memory%20allocation.odt >>>>> We are seeing HW that has recoverable GPU page faults but only for >>>>> compute tasks, and scheduler without semaphores hw for graphics. >>>>> >>>>> So a single driver may have to expose both models to userspace and >>>>> also introduces the problem of how to interoperate between the two >>>>> models on one card. >>>>> >>>>> Dave. >>>> Hmm, yes to begin with it's important to note that this is not a >>>> replacement for new programming models or APIs, This is something that >>>> takes place internally in drivers to mitigate many of the restrictions >>>> that are currently imposed on dma-fence and documented in this and >>>> previous series. It's basically the driver-private narrow completions >>>> Jason suggested in the lockdep patches discussions implemented the same >>>> way as eviction-fences. >>>> >>>> The memory fence API would be local to helpers and middle-layers like >>>> TTM, and the corresponding drivers. The only cross-driver-like >>>> visibility would be that the dma-buf move_notify() callback would not be >>>> allowed to wait on dma-fences or something that depends on a dma-fence. >>> Because we can't preempt (on some engines at least) we already have >>> the requirement that cross driver buffer management can get stuck on a >>> dma-fence. Not even taking into account the horrors we do with >>> userptr, which are cross driver no matter what. Limiting move_notify >>> to memory fences only doesn't work, since the pte clearing might need >>> to wait for a dma_fence first. Hence this becomes a full end-of-batch >>> fence, not just a limited kernel-internal memory fence. >> For non-preemptible hardware the memory fence typically *is* the >> end-of-batch fence. (Unless, as documented, there is a scheduler >> consuming sync-file dependencies in which case the memory fence wait >> needs to be able to break out of that). The key thing is not that we can >> break out of execution, but that we can break out of dependencies, since >> when we're executing all dependecies (modulo semaphores) are already >> fulfilled. That's what's eliminating the deadlocks. >> >>> That's kinda why I think only reasonable option is to toss in the >>> towel and declare dma-fence to be the memory fence (and suck up all >>> the consequences of that decision as uapi, which is kinda where we >>> are), and construct something new&entirely free-wheeling for userspace >>> fencing. But only for engines that allow enough preempt/gpu page >>> faulting to make that possible. Free wheeling userspace fences/gpu >>> semaphores or whatever you want to call them (on windows I think it's >>> monitored fence) only work if you can preempt to decouple the memory >>> fences from your gpu command execution. >>> >>> There's the in-between step of just decoupling the batchbuffer >>> submission prep for hw without any preempt (but a scheduler), but that >>> seems kinda pointless. Modern execbuf should be O(1) fastpath, with >>> all the allocation/mapping work pulled out ahead. vk exposes that >>> model directly to clients, GL drivers could use it internally too, so >>> I see zero value in spending lots of time engineering very tricky >>> kernel code just for old userspace. Much more reasonable to do that in >>> userspace, where we have real debuggers and no panics about security >>> bugs (or well, a lot less, webgl is still a thing, but at least >>> browsers realized you need to container that completely). >> Sure, it's definitely a big chunk of work. I think the big win would be >> allowing memory allocation in dma-fence critical sections. But I >> completely buy the above argument. I just wanted to point out that many >> of the dma-fence restrictions are IMHO fixable, should we need to do >> that for whatever reason. > I'm still not sure that's possible, without preemption at least. We > have 4 edges: > - Kernel has internal depencies among memory fences. We want that to > allow (mild) amounts of overcommit, since that simplifies live so > much. > - Memory fences can block gpu ctx execution (by nature of the memory > simply not being there yet due to our overcommit) > - gpu ctx have (if we allow this) userspace controlled semaphore > dependencies. Of course userspace is expected to not create deadlocks, > but that's only assuming the kernel doesn't inject additional > dependencies. Compute folks really want that. > - gpu ctx can hold up memory allocations if all we have is > end-of-batch fences. And end-of-batch fences are all we have without > preempt, plus if we want backwards compat with the entire current > winsys/compositor ecosystem we need them, which allows us to inject > stuff dependent upon them pretty much anywhere. > > Fundamentally that's not fixable without throwing one of the edges > (and the corresponding feature that enables) out, since no entity has > full visibility into what's going on. E.g. forcing userspace to tell > the kernel about all semaphores just brings up back to the > drm_timeline_syncobj design we have merged right now. And that's imo > no better. Indeed, HW waiting for semaphores without being able to preempt that wait is a no-go. The doc (perhaps naively) assumes nobody is doing that. > > That's kinda why I'm not seeing much benefits in a half-way state: > Tons of work, and still not what userspace wants. And for the full > deal that userspace wants we might as well not change anything with > dma-fences. For that we need a) ctx preempt and b) new entirely > decoupled fences that never feed back into a memory fences and c) are > controlled entirely by userspace. And c) is the really important thing > people want us to provide. > > And once we're ok with dma_fence == memory fences, then enforcing the > strict and painful memory allocation limitations is actually what we > want. Let's hope you're right. My fear is that that might be pretty painful as well. > Cheers, Daniel /Thomas From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96DA0C433DF for ; Wed, 22 Jul 2020 10:31:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A63B20729 for ; Wed, 22 Jul 2020 10:31:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature 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header.b=hVBS9izU; dkim-atps=neutral X-Virus-Scanned: Debian amavisd-new at bahnhof.se Authentication-Results: ste-ftg-msa2.bahnhof.se (amavisd-new); dkim=pass (1024-bit key) header.d=shipmail.org Received: from ste-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (ste-ftg-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qH-zeXr7iqVd; Wed, 22 Jul 2020 12:31:30 +0200 (CEST) Received: from mail1.shipmail.org (h-205-35.A357.priv.bahnhof.se [155.4.205.35]) (Authenticated sender: mb878879) by ste-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id 15D9A3FB79; Wed, 22 Jul 2020 12:31:26 +0200 (CEST) Received: from [192.168.0.100] (h-205-35.A357.priv.bahnhof.se [155.4.205.35]) by mail1.shipmail.org (Postfix) with ESMTPSA id 7E2F3362551; Wed, 22 Jul 2020 12:31:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=shipmail.org; s=mail; t=1595413887; bh=IdgBtUFYB5h3M894fLyGzRGoV7q+2iBbuY3az/yTSL4=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=hVBS9izUpG83NeG87m7+xU3OHQ4U+Wjnh7+3vi2hm9cmFIevDBo+SKzqLY3d6FUNx PCrnVe16MF3td3ncQavKnAgFgKC6DSPBn0crb2FuBw0xFKvaHgNkxnGVHyo/HuWbWP xiy3+ufveb/XDPRihBAsaKMD6mHJ4HNLcpsKNOdk= Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea To: Daniel Vetter References: <20200707201229.472834-4-daniel.vetter@ffwll.ch> <20200709123339.547390-1-daniel.vetter@ffwll.ch> <93b673b7-bb48-96eb-dc2c-bd4f9304000e@shipmail.org> <20200721074157.GB3278063@phenom.ffwll.local> <3603bb71-318b-eb53-0532-9daab62dce86@amd.com> <57a5eb9d-b74f-8ce4-7199-94e911d9b68b@shipmail.org> <805c49b7-f0b3-45dc-5fe3-b352f0971527@shipmail.org> <92393d26-d863-aac6-6d27-53cad6854e13@shipmail.org> From: =?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?= Message-ID: <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> Date: Wed, 22 Jul 2020 12:31:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Felix Kuehling , Daniel Stone , linux-rdma , Intel Graphics Development , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Steve Pronovost , amd-gfx mailing list , Jason Ekstrand , Jesse Natalie , Daniel Vetter , Thomas Hellstrom , Linux Media Mailing List , =?UTF-8?Q?Christian_K=c3=b6nig?= , Mika Kuoppala Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Ck9uIDIwMjAtMDctMjIgMTE6NDUsIERhbmllbCBWZXR0ZXIgd3JvdGU6Cj4gT24gV2VkLCBKdWwg MjIsIDIwMjAgYXQgMTA6MDUgQU0gVGhvbWFzIEhlbGxzdHLDtm0gKEludGVsKQo+IDx0aG9tYXNf b3NAc2hpcG1haWwub3JnPiB3cm90ZToKPj4KPj4gT24gMjAyMC0wNy0yMiAwOToxMSwgRGFuaWVs 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at bahnhof.se Authentication-Results: ste-ftg-msa2.bahnhof.se (amavisd-new); dkim=pass (1024-bit key) header.d=shipmail.org Received: from ste-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (ste-ftg-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qH-zeXr7iqVd; Wed, 22 Jul 2020 12:31:30 +0200 (CEST) Received: from mail1.shipmail.org (h-205-35.A357.priv.bahnhof.se [155.4.205.35]) (Authenticated sender: mb878879) by ste-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id 15D9A3FB79; Wed, 22 Jul 2020 12:31:26 +0200 (CEST) Received: from [192.168.0.100] (h-205-35.A357.priv.bahnhof.se [155.4.205.35]) by mail1.shipmail.org (Postfix) with ESMTPSA id 7E2F3362551; Wed, 22 Jul 2020 12:31:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=shipmail.org; s=mail; t=1595413887; bh=IdgBtUFYB5h3M894fLyGzRGoV7q+2iBbuY3az/yTSL4=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=hVBS9izUpG83NeG87m7+xU3OHQ4U+Wjnh7+3vi2hm9cmFIevDBo+SKzqLY3d6FUNx PCrnVe16MF3td3ncQavKnAgFgKC6DSPBn0crb2FuBw0xFKvaHgNkxnGVHyo/HuWbWP xiy3+ufveb/XDPRihBAsaKMD6mHJ4HNLcpsKNOdk= To: Daniel Vetter References: <20200707201229.472834-4-daniel.vetter@ffwll.ch> <20200709123339.547390-1-daniel.vetter@ffwll.ch> <93b673b7-bb48-96eb-dc2c-bd4f9304000e@shipmail.org> <20200721074157.GB3278063@phenom.ffwll.local> <3603bb71-318b-eb53-0532-9daab62dce86@amd.com> <57a5eb9d-b74f-8ce4-7199-94e911d9b68b@shipmail.org> <805c49b7-f0b3-45dc-5fe3-b352f0971527@shipmail.org> <92393d26-d863-aac6-6d27-53cad6854e13@shipmail.org> From: =?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?= Message-ID: <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> Date: Wed, 22 Jul 2020 12:31:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Subject: Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Felix Kuehling , Daniel Stone , linux-rdma , Intel Graphics Development , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Steve Pronovost , amd-gfx mailing list , Jesse Natalie , Daniel Vetter , Thomas Hellstrom , Linux Media Mailing List , =?UTF-8?Q?Christian_K=c3=b6nig?= , Mika Kuoppala Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Ck9uIDIwMjAtMDctMjIgMTE6NDUsIERhbmllbCBWZXR0ZXIgd3JvdGU6Cj4gT24gV2VkLCBKdWwg MjIsIDIwMjAgYXQgMTA6MDUgQU0gVGhvbWFzIEhlbGxzdHLDtm0gKEludGVsKQo+IDx0aG9tYXNf b3NAc2hpcG1haWwub3JnPiB3cm90ZToKPj4KPj4gT24gMjAyMC0wNy0yMiAwOToxMSwgRGFuaWVs IFZldHRlciB3cm90ZToKPj4+IE9uIFdlZCwgSnVsIDIyLCAyMDIwIGF0IDg6NDUgQU0gVGhvbWFz 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(amavisd-new); dkim=pass (1024-bit key) header.d=shipmail.org Received: from ste-pvt-msa2.bahnhof.se ([127.0.0.1]) by localhost (ste-ftg-msa2.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qH-zeXr7iqVd; Wed, 22 Jul 2020 12:31:30 +0200 (CEST) Received: from mail1.shipmail.org (h-205-35.A357.priv.bahnhof.se [155.4.205.35]) (Authenticated sender: mb878879) by ste-pvt-msa2.bahnhof.se (Postfix) with ESMTPA id 15D9A3FB79; Wed, 22 Jul 2020 12:31:26 +0200 (CEST) Received: from [192.168.0.100] (h-205-35.A357.priv.bahnhof.se [155.4.205.35]) by mail1.shipmail.org (Postfix) with ESMTPSA id 7E2F3362551; Wed, 22 Jul 2020 12:31:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=shipmail.org; s=mail; t=1595413887; bh=IdgBtUFYB5h3M894fLyGzRGoV7q+2iBbuY3az/yTSL4=; h=Subject:To:Cc:References:From:Date:In-Reply-To:From; b=hVBS9izUpG83NeG87m7+xU3OHQ4U+Wjnh7+3vi2hm9cmFIevDBo+SKzqLY3d6FUNx PCrnVe16MF3td3ncQavKnAgFgKC6DSPBn0crb2FuBw0xFKvaHgNkxnGVHyo/HuWbWP xiy3+ufveb/XDPRihBAsaKMD6mHJ4HNLcpsKNOdk= Subject: Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf.rst: Document why indefinite fences are a bad idea To: Daniel Vetter References: <20200707201229.472834-4-daniel.vetter@ffwll.ch> <20200709123339.547390-1-daniel.vetter@ffwll.ch> <93b673b7-bb48-96eb-dc2c-bd4f9304000e@shipmail.org> <20200721074157.GB3278063@phenom.ffwll.local> <3603bb71-318b-eb53-0532-9daab62dce86@amd.com> <57a5eb9d-b74f-8ce4-7199-94e911d9b68b@shipmail.org> <805c49b7-f0b3-45dc-5fe3-b352f0971527@shipmail.org> <92393d26-d863-aac6-6d27-53cad6854e13@shipmail.org> From: =?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?= Message-ID: <8fd999f2-cbf6-813c-6ad4-131948fb5cc5@shipmail.org> Date: Wed, 22 Jul 2020 12:31:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Felix Kuehling , Daniel Stone , linux-rdma , Intel Graphics Development , Maarten Lankhorst , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Steve Pronovost , amd-gfx mailing list , Jason Ekstrand , Jesse Natalie , Daniel Vetter , Thomas Hellstrom , Linux Media Mailing List , Dave Airlie , =?UTF-8?Q?Christian_K=c3=b6nig?= , Mika Kuoppala Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Ck9uIDIwMjAtMDctMjIgMTE6NDUsIERhbmllbCBWZXR0ZXIgd3JvdGU6Cj4gT24gV2VkLCBKdWwg MjIsIDIwMjAgYXQgMTA6MDUgQU0gVGhvbWFzIEhlbGxzdHLDtm0gKEludGVsKQo+IDx0aG9tYXNf b3NAc2hpcG1haWwub3JnPiB3cm90ZToKPj4KPj4gT24gMjAyMC0wNy0yMiAwOToxMSwgRGFuaWVs IFZldHRlciB3cm90ZToKPj4+IE9uIFdlZCwgSnVsIDIyLCAyMDIwIGF0IDg6NDUgQU0gVGhvbWFz IEhlbGxzdHLDtm0gKEludGVsKQo+Pj4gPHRob21hc19vc0BzaGlwbWFpbC5vcmc+IHdyb3RlOgo+ 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