[U-Boot] [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes

[U-Boot] [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes

[Vikas Manocha]

This patchset:
- removes sram polling while reading/writing from flash.
- fixes trigger base & transfer start address register programming. This fix
superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger
address setting"
- adds support to get fifo width from device tree

Vikas Manocha (6):
  spi: cadence_qspi: remove sram polling from flash read
  spi: cadence_qspi: remove sram polling from flash write
  spi: cadence_qspi: move trigger base configuration in init
  spi: cadence_qspi: fix indirect read/write start address
  spi: cadence_qspi: fix base trigger address & transfer start address
  spi: cadence_qspi: get fifo width from device tree

 arch/arm/dts/socfpga.dtsi      |    2 +
 arch/arm/dts/stv0991.dts       |    4 +-
 drivers/spi/cadence_qspi.c     |   14 +++--
 drivers/spi/cadence_qspi.h     |    6 +-
 drivers/spi/cadence_qspi_apb.c |  124 +++++++++-------------------------------
 5 files changed, 43 insertions(+), 107 deletions(-)

-- 
1.7.9.5

[U-Boot] [PATCH 1/6] spi: cadence_qspi: remove sram polling from flash read

[Vikas Manocha]

There is no need to check for sram fill level. If sram is empty, cpu
will go in the wait state till the time data is available from flash.

Also Relying on SRAM fill level only for deciding when the data should be
fetched from the local SRAM is not most efficient approach, particulary
if we are working on high data rates.

It should be noticed that after one SRAM word is collected, the information is
forwarded into system domain and then synchronized into register domain (apb).
If we are using slow APB and AHB clks, SRAM fill level might not be up-to-dated
because of latency cycles needed for synchronization. For example in case we are
getting SRAM fill level equal to 10 locations but in reality there were 2
another words completed and actual level is 12 but information may not be
synchronized yet because of the synchronization latency on APB domain.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 drivers/spi/cadence_qspi_apb.c |   45 +++++-----------------------------------
 1 file changed, 5 insertions(+), 40 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index a168912..32cbc23 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -191,7 +191,7 @@ static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 	return addr;
 }
 
-static void cadence_qspi_apb_read_fifo_data(void *dest,
+static int cadence_qspi_apb_read_fifo_data(void *dest,
 	const void *src_ahb_addr, unsigned int bytes)
 {
 	unsigned int temp;
@@ -210,7 +210,7 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
 		memcpy(dest_ptr, &temp, remaining);
 	}
 
-	return;
+	return 0;
 }
 
 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
@@ -240,42 +240,6 @@ static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
 	return;
 }
 
-/* Read from SRAM FIFO with polling SRAM fill level. */
-static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
-			const void *src_addr,  unsigned int num_bytes)
-{
-	unsigned int remaining = num_bytes;
-	unsigned int retry;
-	unsigned int sram_level = 0;
-	unsigned char *dest = (unsigned char *)dest_addr;
-
-	while (remaining > 0) {
-		retry = CQSPI_REG_RETRY;
-		while (retry--) {
-			sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
-			if (sram_level)
-				break;
-			udelay(1);
-		}
-
-		if (!retry) {
-			printf("QSPI: No receive data after polling for %d times\n",
-			       CQSPI_REG_RETRY);
-			return -1;
-		}
-
-		sram_level *= CQSPI_FIFO_WIDTH;
-		sram_level = sram_level > remaining ? remaining : sram_level;
-
-		/* Read data from FIFO. */
-		cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
-		dest += sram_level;
-		remaining -= sram_level;
-		udelay(1);
-	}
-	return 0;
-}
-
 /* Write to SRAM FIFO with polling SRAM fill level. */
 static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
 				const void *src_addr, unsigned int num_bytes)
@@ -751,9 +715,10 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 	/* Start the indirect read transfer */
 	writel(CQSPI_REG_INDIRECTRD_START_MASK,
 	       plat->regbase + CQSPI_REG_INDIRECTRD);
+	udelay(1);
 
-	if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
-				     (const void *)plat->ahbbase, rxlen))
+	if (cadence_qspi_apb_read_fifo_data((void*)rxbuf,
+				(const void *) plat->ahbbase, rxlen))
 		goto failrd;
 
 	/* Check flash indirect controller */
-- 
1.7.9.5

[U-Boot] [PATCH 2/6] spi: cadence_qspi: remove sram polling from flash write

[Vikas Manocha]

There is no need to poll sram level before writing to flash, data going to SRAM
till sram is full, after that backpressure will take over.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 drivers/spi/cadence_qspi_apb.c |   63 ++++++++++------------------------------
 1 file changed, 16 insertions(+), 47 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 32cbc23..313f6ac 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -213,66 +213,35 @@ static int cadence_qspi_apb_read_fifo_data(void *dest,
 	return 0;
 }
 
-static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
-	const void *src, unsigned int bytes)
-{
-	unsigned int temp=0;
-	int i;
-	int remaining = bytes;
-	unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
-	unsigned int *src_ptr = (unsigned int *)src;
-
-	while (remaining >= CQSPI_FIFO_WIDTH) {
-		for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
-			writel(*(src_ptr+i), dest_ptr+i);
-		src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
-		remaining -= CQSPI_FIFO_WIDTH;
-	}
-	if (remaining)
-	{
-		/* dangling bytes */
-		i = remaining/sizeof(dest_ptr);
-		memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
-		writel(temp, dest_ptr+i);
-		for (--i; i >= 0; i--)
-			writel(*(src_ptr+i), dest_ptr+i);
-	}
-	return;
-}
-
-/* Write to SRAM FIFO with polling SRAM fill level. */
 static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
 				const void *src_addr, unsigned int num_bytes)
 {
-	const void *reg_base = plat->regbase;
-	void *dest_addr = plat->ahbbase;
-	unsigned int retry = CQSPI_REG_RETRY;
-	unsigned int sram_level;
+	int i = 0;
+	unsigned int *dest_addr = plat->trigger_base;
 	unsigned int wr_bytes;
-	unsigned char *src = (unsigned char *)src_addr;
+	unsigned int *src_ptr = (unsigned int *)src_addr;
 	int remaining = num_bytes;
 	unsigned int page_size = plat->page_size;
-	unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
 
 	while (remaining > 0) {
-		retry = CQSPI_REG_RETRY;
-		while (retry--) {
-			sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
-			if (sram_level <= sram_threshold_words)
-				break;
-		}
-		if (!retry) {
-			printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
-			       sram_level, sram_threshold_words);
-			return -1;
-		}
 		/* Write a page or remaining bytes. */
 		wr_bytes = (remaining > page_size) ?
 					page_size : remaining;
 
-		cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
-		src += wr_bytes;
 		remaining -= wr_bytes;
+		while (wr_bytes >= CQSPI_FIFO_WIDTH) {
+			for (i = 0; i < CQSPI_FIFO_WIDTH/sizeof(dest_addr); i++)
+				writel(*(src_ptr+i), dest_addr+i);
+			src_ptr += CQSPI_FIFO_WIDTH/sizeof(dest_addr);
+			wr_bytes -= CQSPI_FIFO_WIDTH;
+		}
+		if (wr_bytes)
+		{
+			/* dangling bytes */
+			i = wr_bytes/sizeof(dest_addr);
+			for (i = wr_bytes/sizeof(dest_addr); i >= 0; i--)
+				writel(*(src_ptr+i), dest_addr+i);
+		}
 	}
 
 	return 0;
-- 
1.7.9.5

[U-Boot] [PATCH 3/6] spi: cadence_qspi: move trigger base configuration in init

[Vikas Manocha]

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 drivers/spi/cadence_qspi_apb.c |    6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 313f6ac..515d88e 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -467,6 +467,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 
 	/* Indirect mode configurations */
 	writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
+	writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
 	/* Disable all interrupts */
 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
@@ -626,9 +627,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 		/* for normal read (only ramtron as of now) */
 		addr_bytes = cmdlen - 1;
 
-	/* Setup the indirect trigger address */
-	writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
-
 	/* Configure the opcode */
 	rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 
@@ -723,8 +721,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 		       cmdlen, (unsigned int)cmdbuf);
 		return -EINVAL;
 	}
-	/* Setup the indirect trigger address */
-	writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
 	/* Configure the opcode */
 	reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
-- 
1.7.9.5

[U-Boot] [PATCH 4/6] spi: cadence_qspi: fix indirect read/write start address

[Vikas Manocha]

Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 drivers/spi/cadence_qspi_apb.c |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 515d88e..7174f7c 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -637,7 +637,8 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 
 	/* Get address */
 	addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
-	writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+	writel((u32)plat->ahbbase + addr_value, \
+			plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 
 	/* The remaining lenght is dummy bytes. */
 	dummy_bytes = cmdlen - addr_bytes - 1;
@@ -728,7 +729,8 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 
 	/* Setup write address. */
 	reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
-	writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
+	writel((u32)plat->ahbbase + reg, \
+			plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 
 	reg = readl(plat->regbase + CQSPI_REG_SIZE);
 	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
-- 
1.7.9.5

[U-Boot] [PATCH 5/6] spi: cadence_qspi: fix base trigger address & transfer start address

[Vikas Manocha]

This patch is to separate the base trigger from the read/write transfer start
addresses.

Base trigger register address (0x1c register) corresponds to the
address which should be put on AHB bus to handle indirect transfer
triggered before.
To handle indirect transfer we need to issue addresses from (value of 0x1c) to
(value of 0x1c) + 15*4 ("4" corresponds to size of SRAM location).
There are no obstacles in issuing const address just equal to 0x1c. Important
thing to note is that indirect trigger address has nothing in common with your
physical or mapped NOR Flash address.

Transfer read/write start addresses (offset 0x68/0x78)should be programmed with
the absolute flash address to be read/written.

plat->ahbbase has been renamed to plat->flashbase for clarity.
plat->triggerbase is added in device tree for mapped spi flash address.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 arch/arm/dts/socfpga.dtsi      |    1 +
 arch/arm/dts/stv0991.dts       |    3 ++-
 drivers/spi/cadence_qspi.c     |   13 +++++++------
 drivers/spi/cadence_qspi.h     |    5 +++--
 drivers/spi/cadence_qspi_apb.c |    9 +++++----
 5 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 9b12420..c957f44 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -634,6 +634,7 @@
 			#size-cells = <0>;
 			reg = <0xff705000 0x1000>,
 				<0xffa00000 0x1000>;
+				<0x00000000 0x0010>;
 			interrupts = <0 151 4>;
 			clocks = <&qspi_clk>;
 			ext-decoder = <0>;  /* external decoder */
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index 556df82..f30a818 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -30,7 +30,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x80203000 0x100>,
-				<0x40000000 0x1000000>;
+				<0x40000000 0x1000000>,
+				<0x40000000 0x0000010>;
 			clocks = <3750000>;
 			ext-decoder = <0>; /* external decoder */
 			num-cs = <4>;
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 34a0f46..8b6de4f 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -150,7 +150,7 @@ static int cadence_spi_probe(struct udevice *bus)
 	struct cadence_spi_priv *priv = dev_get_priv(bus);
 
 	priv->regbase = plat->regbase;
-	priv->ahbbase = plat->ahbbase;
+	priv->flashbase = plat->flashbase;
 
 	if (!priv->qspi_is_init) {
 		cadence_qspi_apb_controller_init(plat);
@@ -278,7 +278,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 	const void *blob = gd->fdt_blob;
 	int node = bus->of_offset;
 	int subnode;
-	u32 data[4];
+	u32 data[6];
 	int ret;
 
 	/* 2 base addresses are needed, lets get them from the DT */
@@ -289,7 +289,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 	}
 
 	plat->regbase = (void *)data[0];
-	plat->ahbbase = (void *)data[2];
+	plat->flashbase = (void *)data[2];
+	plat->trigger_base = (void *)data[4];
 
 	/* Use 500KHz as a suitable default */
 	plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
@@ -311,9 +312,9 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 	plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
 	plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
 
-	debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
-	      __func__, plat->regbase, plat->ahbbase, plat->max_hz,
-	      plat->page_size);
+	debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \
+		page-size=%d\n", __func__, plat->regbase, plat->flashbase, \
+		plat->trigger_base, plat->max_hz, plat->page_size);
 
 	return 0;
 }
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 98e57aa..7341339 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -17,7 +17,8 @@
 struct cadence_spi_platdata {
 	unsigned int	max_hz;
 	void		*regbase;
-	void		*ahbbase;
+	void		*flashbase;
+	void		*trigger_base;
 
 	u32		page_size;
 	u32		block_size;
@@ -30,7 +31,7 @@ struct cadence_spi_platdata {
 
 struct cadence_spi_priv {
 	void		*regbase;
-	void		*ahbbase;
+	void		*flashbase;
 	size_t		cmd_len;
 	u8		cmd_buf[32];
 	size_t		data_len;
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 7174f7c..e6ff0e0 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -467,7 +467,8 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 
 	/* Indirect mode configurations */
 	writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
-	writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
+	writel((u32)plat->trigger_base,
+			plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
 	/* Disable all interrupts */
 	writel(0, plat->regbase + CQSPI_REG_IRQMASK);
@@ -637,7 +638,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 
 	/* Get address */
 	addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
-	writel((u32)plat->ahbbase + addr_value, \
+	writel((u32)plat->flashbase + addr_value, \
 			plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 
 	/* The remaining lenght is dummy bytes. */
@@ -686,7 +687,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 	udelay(1);
 
 	if (cadence_qspi_apb_read_fifo_data((void*)rxbuf,
-				(const void *) plat->ahbbase, rxlen))
+				(const void *) plat->trigger_base, rxlen))
 		goto failrd;
 
 	/* Check flash indirect controller */
@@ -729,7 +730,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 
 	/* Setup write address. */
 	reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
-	writel((u32)plat->ahbbase + reg, \
+	writel((u32)plat->flashbase + reg, \
 			plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 
 	reg = readl(plat->regbase + CQSPI_REG_SIZE);
-- 
1.7.9.5

[U-Boot] [PATCH 6/6] spi: cadence_qspi: get fifo width from device tree

[Vikas Manocha]

Fifo width could be different on different socs, e.g. stv0991 & altera soc
have different fifo width.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
---
 arch/arm/dts/socfpga.dtsi      |    1 +
 arch/arm/dts/stv0991.dts       |    1 +
 drivers/spi/cadence_qspi.c     |    1 +
 drivers/spi/cadence_qspi.h     |    1 +
 drivers/spi/cadence_qspi_apb.c |   13 ++++---------
 5 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index c957f44..48bbbb3 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -641,6 +641,7 @@
 			num-cs = <4>;
 			fifo-depth = <128>;
 			sram-size = <128>;
+			fifo-width = <4>;
 			bus-num = <2>;
 			status = "disabled";
 		};
diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index f30a818..96583b1 100644
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -37,6 +37,7 @@
 			num-cs = <4>;
 			fifo-depth = <256>;
 			sram-size = <256>;
+			fifo-width = <8>;
 			bus-num = <0>;
 			status = "okay";
 
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 8b6de4f..71594ed 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -311,6 +311,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
 	plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
 	plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
 	plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
+	plat->fifo_width = fdtdec_get_int(blob, node, "fifo-width", 4);
 
 	debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \
 		page-size=%d\n", __func__, plat->regbase, plat->flashbase, \
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 7341339..91f38f1 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -27,6 +27,7 @@ struct cadence_spi_platdata {
 	u32		tchsh_ns;
 	u32		tslch_ns;
 	u32		sram_size;
+	u32		fifo_width;
 };
 
 struct cadence_spi_priv {
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e6ff0e0..b37addf 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -34,8 +34,6 @@
 #define CQSPI_REG_RETRY				(10000)
 #define CQSPI_POLL_IDLE_RETRY			(3)
 
-#define CQSPI_FIFO_WIDTH			(4)
-
 #define CQSPI_REG_SRAM_THRESHOLD_WORDS		(50)
 
 /* Transfer mode */
@@ -48,9 +46,6 @@
 #define CQSPI_DUMMY_CLKS_PER_BYTE		(8)
 #define CQSPI_DUMMY_BYTES_MAX			(4)
 
-
-#define CQSPI_REG_SRAM_FILL_THRESHOLD	\
-	((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
 /****************************************************************************
  * Controller's configuration and status register (offset from QSPI_BASE)
  ****************************************************************************/
@@ -229,11 +224,11 @@ static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
 					page_size : remaining;
 
 		remaining -= wr_bytes;
-		while (wr_bytes >= CQSPI_FIFO_WIDTH) {
-			for (i = 0; i < CQSPI_FIFO_WIDTH/sizeof(dest_addr); i++)
+		while (wr_bytes >= plat->fifo_width) {
+			for (i = 0; i < plat->fifo_width/sizeof(dest_addr); i++)
 				writel(*(src_ptr+i), dest_addr+i);
-			src_ptr += CQSPI_FIFO_WIDTH/sizeof(dest_addr);
-			wr_bytes -= CQSPI_FIFO_WIDTH;
+			src_ptr += plat->fifo_width/sizeof(dest_addr);
+			wr_bytes -= plat->fifo_width;
 		}
 		if (wr_bytes)
 		{
-- 
1.7.9.5

[U-Boot] [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes

[Vikas MANOCHA]

Hello All,

I just figured out that this patchset has dependency on another patchset under review. I am not sure how to handle situations like this.
I can think of following options, please let me know if anyone of these is ok:

- I send the next version of my previous patchset (under review) with addition of this patchset. With it, all the patches will apply on master.
- wait for the previous patchset to get in mainline....(might take some time).

Rgds,
Vikas

> -----Original Message-----
> From: Vikas MANOCHA
> Sent: Monday, June 15, 2015 11:19 AM
> To: u-boot at lists.denx.de; sr at denx.de; grmoore at opensource.altera.com;
> dinguyen at opensource.altera.com
> Cc: Vikas MANOCHA
> Subject: [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes
> 
> This patchset:
> - removes sram polling while reading/writing from flash.
> - fixes trigger base & transfer start address register programming. This fix
> superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb
> trigger address setting"
> - adds support to get fifo width from device tree
> 
> Vikas Manocha (6):
>   spi: cadence_qspi: remove sram polling from flash read
>   spi: cadence_qspi: remove sram polling from flash write
>   spi: cadence_qspi: move trigger base configuration in init
>   spi: cadence_qspi: fix indirect read/write start address
>   spi: cadence_qspi: fix base trigger address & transfer start address
>   spi: cadence_qspi: get fifo width from device tree
> 
>  arch/arm/dts/socfpga.dtsi      |    2 +
>  arch/arm/dts/stv0991.dts       |    4 +-
>  drivers/spi/cadence_qspi.c     |   14 +++--
>  drivers/spi/cadence_qspi.h     |    6 +-
>  drivers/spi/cadence_qspi_apb.c |  124 +++++++++-------------------------------
>  5 files changed, 43 insertions(+), 107 deletions(-)
> 
> --
> 1.7.9.5

[U-Boot] [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes

[Jagan Teki]

On 16 June 2015 at 00:21, Vikas MANOCHA <vikas.manocha@st.com> wrote:
> Hello All,
>
> I just figured out that this patchset has dependency on another patchset under review. I am not sure how to handle situations like this.
> I can think of following options, please let me know if anyone of these is ok:
>
> - I send the next version of my previous patchset (under review) with addition of this patchset. With it, all the patches will apply on master.
> - wait for the previous patchset to get in mainline....(might take some time).

Just create the patches on top of master[1] and add the subject-prefix
as PATCH RESEND.
Pls- try to work on master always for avoiding dependencies.

[1] http://git.denx.de/?p=u-boot.git;a=summary

>
> Rgds,
> Vikas
>
>> -----Original Message-----
>> From: Vikas MANOCHA
>> Sent: Monday, June 15, 2015 11:19 AM
>> To: u-boot at lists.denx.de; sr at denx.de; grmoore at opensource.altera.com;
>> dinguyen at opensource.altera.com
>> Cc: Vikas MANOCHA
>> Subject: [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes
>>
>> This patchset:
>> - removes sram polling while reading/writing from flash.
>> - fixes trigger base & transfer start address register programming. This fix
>> superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb
>> trigger address setting"
>> - adds support to get fifo width from device tree
>>
>> Vikas Manocha (6):
>>   spi: cadence_qspi: remove sram polling from flash read
>>   spi: cadence_qspi: remove sram polling from flash write
>>   spi: cadence_qspi: move trigger base configuration in init
>>   spi: cadence_qspi: fix indirect read/write start address
>>   spi: cadence_qspi: fix base trigger address & transfer start address
>>   spi: cadence_qspi: get fifo width from device tree
>>
>>  arch/arm/dts/socfpga.dtsi      |    2 +
>>  arch/arm/dts/stv0991.dts       |    4 +-
>>  drivers/spi/cadence_qspi.c     |   14 +++--
>>  drivers/spi/cadence_qspi.h     |    6 +-
>>  drivers/spi/cadence_qspi_apb.c |  124 +++++++++-------------------------------
>>  5 files changed, 43 insertions(+), 107 deletions(-)

thanks!
-- 
Jagan | Openedev.

[U-Boot] [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect read-writes

[Vikas MANOCHA]

Thanks Jagan.
Rgds,
Vikas

> -----Original Message-----
> From: Jagan Teki [mailto:jteki at openedev.com]
> Sent: Monday, June 15, 2015 12:31 PM
> To: Vikas MANOCHA
> Cc: u-boot at lists.denx.de; sr at denx.de; grmoore at opensource.altera.com;
> dinguyen at opensource.altera.com
> Subject: Re: [U-Boot] [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect
> read-writes
> 
> On 16 June 2015 at 00:21, Vikas MANOCHA <vikas.manocha@st.com> wrote:
> > Hello All,
> >
> > I just figured out that this patchset has dependency on another patchset
> under review. I am not sure how to handle situations like this.
> > I can think of following options, please let me know if anyone of these is
> ok:
> >
> > - I send the next version of my previous patchset (under review) with
> addition of this patchset. With it, all the patches will apply on master.
> > - wait for the previous patchset to get in mainline....(might take some
> time).
> 
> Just create the patches on top of master[1] and add the subject-prefix as
> PATCH RESEND.
> Pls- try to work on master always for avoiding dependencies.
> 
> [1] http://git.denx.de/?p=u-boot.git;a=summary
> 
> >
> > Rgds,
> > Vikas
> >
> >> -----Original Message-----
> >> From: Vikas MANOCHA
> >> Sent: Monday, June 15, 2015 11:19 AM
> >> To: u-boot at lists.denx.de; sr at denx.de;
> grmoore at opensource.altera.com;
> >> dinguyen at opensource.altera.com
> >> Cc: Vikas MANOCHA
> >> Subject: [PATCH 0/6] spi: cadence_qspi: optimize & fix indirect
> >> read-writes
> >>
> >> This patchset:
> >> - removes sram polling while reading/writing from flash.
> >> - fixes trigger base & transfer start address register programming.
> >> This fix superseeds the previous patch "spi: cadence_qspi: Fix the
> >> indirect ahb trigger address setting"
> >> - adds support to get fifo width from device tree
> >>
> >> Vikas Manocha (6):
> >>   spi: cadence_qspi: remove sram polling from flash read
> >>   spi: cadence_qspi: remove sram polling from flash write
> >>   spi: cadence_qspi: move trigger base configuration in init
> >>   spi: cadence_qspi: fix indirect read/write start address
> >>   spi: cadence_qspi: fix base trigger address & transfer start address
> >>   spi: cadence_qspi: get fifo width from device tree
> >>
> >>  arch/arm/dts/socfpga.dtsi      |    2 +
> >>  arch/arm/dts/stv0991.dts       |    4 +-
> >>  drivers/spi/cadence_qspi.c     |   14 +++--
> >>  drivers/spi/cadence_qspi.h     |    6 +-
> >>  drivers/spi/cadence_qspi_apb.c |  124
> >> +++++++++-------------------------------
> >>  5 files changed, 43 insertions(+), 107 deletions(-)
> 
> thanks!
> --
> Jagan | Openedev.