From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vikas MANOCHA Date: Wed, 24 Jun 2015 23:20:07 +0200 Subject: [U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix for FIFO width In-Reply-To: References: <1433899499-17753-1-git-send-email-vikas.manocha@st.com> <9026814FBF99304F9FA3AC3FB72F3E2F016A84F8@SAFEX1MAIL4.st.com> <557ACC2D.5000503@denx.de> <9026814FBF99304F9FA3AC3FB72F3E2F016A87DD@SAFEX1MAIL4.st.com> <558A81D6.6030403@denx.de> <9026814FBF99304F9FA3AC3FB72F3E2F016C3591@SAFEX1MAIL4.st.com> Message-ID: <9026814FBF99304F9FA3AC3FB72F3E2F016C359C@SAFEX1MAIL4.st.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Thanks Jagan, > -----Original Message----- > From: Jagan Teki [mailto:jteki at openedev.com] > Sent: Wednesday, June 24, 2015 11:54 AM > To: Vikas MANOCHA > Cc: Stefan Roese; u-boot at lists.denx.de; grmoore at opensource.altera.com > Subject: Re: [U-Boot] [PATCH 0/3] spi: cadence_qspi: sram depth from DT & > fix for FIFO width > > On 24 June 2015 at 23:43, Vikas MANOCHA wrote: > > Thanks Stefan, > > Adding Jagan to apply the patchset. > > I saw checkpatch.pl errors/warnings with 1 and 3 patches, please check it > those and resend. Yes for Patch3, I will fix it & send the v2. Patch1 has one check info (Alignment should match open parenthesis) I think it should be ignored.. Rgds, Vikas > Anyway I will apply these on master-next for next releases, is that fine? > > > > >> -----Original Message----- > >> From: Stefan Roese [mailto:sr at denx.de] > >> Sent: Wednesday, June 24, 2015 3:09 AM > >> To: Vikas MANOCHA > >> Cc: u-boot at lists.denx.de; grmoore at opensource.altera.com; > >> dinguyen at opensource.altera.com > >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & fix > >> for FIFO width > >> > >> Hi Vikas, > >> > >> On 23.06.2015 16:48, Vikas MANOCHA wrote: > >> >> -----Original Message----- > >> >> From: Stefan Roese [mailto:sr at denx.de] > >> >> Sent: Friday, June 12, 2015 5:10 AM > >> >> To: Vikas MANOCHA; u-boot at lists.denx.de; > >> >> grmoore at opensource.altera.com; dinguyen at opensource.altera.com > >> >> Subject: Re: [PATCH 0/3] spi: cadence_qspi: sram depth from DT & > >> >> fix for FIFO width > >> >> > >> >> Hi Vikas, > >> >> > >> >> On 11.06.2015 21:16, Vikas MANOCHA wrote: > >> >>> Any comments on the patchset. > >> >> > >> >> I'll test them next week on a SoCFPGA based board and will comment > >> >> then again. > >> > > >> > Can you please test this patchset also. > >> > >> Okay. I've now tested this 3 patch series as well on top of mainline. > >> And SPI NOR seems to work just fine with this one applied. Not errors > >> and the write/read/compare test also works okay. > > thanks! > -- > Jagan | openedev.