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Subject: Re: [PATCH] arm64: tegra: Properly size register regions for GPU on
 Tegra194
To:     Thierry Reding <thierry.reding@gmail.com>
CC:     Jon Hunter <jonathanh@nvidia.com>, <linux-tegra@vger.kernel.org>
References: <20200721151055.253644-1-thierry.reding@gmail.com>
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From:   Terje Bergstrom <tbergstrom@nvidia.com>
Message-ID: <903f1237-82d2-7a32-4ac6-ee780857c19e@nvidia.com>
Date:   Fri, 24 Jul 2020 16:29:20 -0700
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On 7/21/2020 8:10 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather
> than 256 MiB.
>
> Reported-by: Terje Bergstr=C3=B6m <tbergstrom@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>   arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/d=
ts/nvidia/tegra194.dtsi
> index 48160f48003a..fc36d683049b 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -1398,8 +1398,8 @@ sor3: sor@15bc0000 {
>  =20
>   		gpu@17000000 {
>   			compatible =3D "nvidia,gv11b";
> -			reg =3D <0x17000000 0x10000000>,
> -			      <0x18000000 0x10000000>;
> +			reg =3D <0x17000000 0x1000000>,
> +			      <0x18000000 0x1000000>;
>   			interrupts =3D <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
>   			interrupt-names =3D "stall", "nonstall";

Looks good to me.

Reviewed-By: Terje Bergstr=C3=B6m <tbergstrom@nvidia.com>

Terje