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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id r5sm18275804wrm.79.2021.09.21.02.45.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Sep 2021 02:45:26 -0700 (PDT) Message-ID: <90d882ac-968e-26f0-e5a4-8a2a401119cc@amsat.org> Date: Tue, 21 Sep 2021 11:45:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 Subject: Re: [PATCH v5 01/31] target/arm: Implement arm_v7m_cpu_has_work() Content-Language: en-US To: Peter Maydell References: <20210920214447.2998623-1-f4bug@amsat.org> <20210920214447.2998623-2-f4bug@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Davidsaver , Richard Henderson , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/21/21 11:34, Peter Maydell wrote: > On Mon, 20 Sept 2021 at 22:44, Philippe Mathieu-Daudé wrote: >> >> Implement SysemuCPUOps::has_work() handler for the ARM v7M CPU. >> >> See the comments added in commit 7ecdaa4a963 ("armv7m: Fix >> condition check for taking exceptions") which eventually >> forgot to implement this has_work() handler: > > Huh? M-profile and A-profile share the same arm_cpu_has_work() > function. Some of the checks the code there does are perhaps > unnecessary for M-profile, but they're harmless. > >> * ARMv7-M interrupt masking works differently than -A or -R. >> * There is no FIQ/IRQ distinction. >> >> The NVIC signal any pending interrupt by raising ARM_CPU_IRQ >> (see commit 56b7c66f498: "armv7m: QOMify the armv7m container") >> which ends setting the CPU_INTERRUPT_HARD bit in interrupt_request. >> >> Thus arm_v7m_cpu_has_work() implementation is thus quite trivial, >> we simply need to check for this bit. >> >> Cc: Peter Maydell >> Cc: Michael Davidsaver >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> target/arm/cpu_tcg.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c >> index 0d5adccf1a7..da348938407 100644 >> --- a/target/arm/cpu_tcg.c >> +++ b/target/arm/cpu_tcg.c >> @@ -23,6 +23,11 @@ >> #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) >> >> #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) >> +static bool arm_v7m_cpu_has_work(CPUState *cs) >> +{ >> + return cs->interrupt_request & CPU_INTERRUPT_HARD; >> +} > > This seems to be missing at least the check on > cpu->power_state and the CPU_INTERRUPT_EXITTB test. > > Is there any reason why we shouldn't just continue to > share the same function between A and M profile, and avoid > the extra function and the ifdefs ? The only reason I can think of is I should have been resting instead of posting this patch :/ I'll re-use arm_cpu_has_work() which is, as you said, harmless and safer.