From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btyfd-0007wN-BD for qemu-devel@nongnu.org; Tue, 11 Oct 2016 11:08:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1btyfY-00007G-Vm for qemu-devel@nongnu.org; Tue, 11 Oct 2016 11:08:44 -0400 Received: from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:33598) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btyfY-00007B-Qo for qemu-devel@nongnu.org; Tue, 11 Oct 2016 11:08:40 -0400 Received: by mail-qk0-x241.google.com with SMTP id f128so1038283qkb.0 for ; Tue, 11 Oct 2016 08:08:40 -0700 (PDT) Sender: Richard Henderson References: <1475316333-9776-1-git-send-email-atar4qemu@gmail.com> <1475316333-9776-4-git-send-email-atar4qemu@gmail.com> <8028f779-8a8f-0427-418e-fe61e044ba43@twiddle.net> From: Richard Henderson Message-ID: <91251f7d-94ef-e3cd-34cc-859c88de2604@twiddle.net> Date: Tue, 11 Oct 2016 10:08:37 -0500 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 03/29] target-sparc: add UA2005 TTE bit #defines List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko Cc: Mark Cave-Ayland , qemu-devel On 10/11/2016 08:51 AM, Artyom Tarasenko wrote: > On Tue, Oct 11, 2016 at 7:50 AM, Richard Henderson wrote: >> On 10/10/2016 04:45 PM, Artyom Tarasenko wrote: >>>> >>>> Hmm. Would it make more sense to reorg these as >>>> >>>> TTE_US1_* >>>> TTE_UA2005_* >>>> >>>> with some duplication for the bits that are shared? >>>> As is, it's pretty hard to tell which actually change... >>> >>> >>> All of them :-) >>> I'm not sure about renaming: the US1 format is still used in T1 on the >>> read >>> access. >>> >>> On the other hand, it's not used in T2. And then again we don't have the >>> T2 >>> emulation yet. >> >> >> Oh my. Different on T2 as well? > > T2 has more used bits, and can not use the US1 format, I think. > >> I wonder if it would make sense to have different functions with which to >> fill in the CPUClass hooks (or invent new SPARCCPUClass hooks as necessary) >> for the major entry points. >> >> E.g. sparc_cpu_handle_mmu_fault or get_physical_address could be hooked, so >> that the choice of how to handle the tlb miss is chosen at startup time, and >> not during each fault. One can arrange subroutines as necessary to share >> code between the alternate routines, such as when T1 needs to use parts of >> US1. > > Yes, I plan to do it once I get to T2 emulation. Ok. >> Similarly for out-of-line ASI handling, which is already beyond messy, with >> handling for all cpus thrown in the same switch statement. > > Yes. I think we need to split SPARCv9 standard ASIs from CPU-specific > ones, call cpu-specific handlers first and standard handler > afterwards. > But not in this series. Fair enough. What I would most like to see, for QEMU, is an artificial sun4v compatible machine that implements a "hardware" page table walk. I.e. no use of SparcTLBEntry, but walking the page tables directly. Because QEMU can then satisfy a page lookup internally, without having to longjmp out of a memory reference in progress in order to restart the cpu for the software TLB miss handler, the emulation runs about 30-50% faster. At least that has been my experience emulating Alpha vs MIPS. It would require custom roms, but those should be fairly easy to modify from the existing source. r~