Re: [PATCH v5 01/10] hw/intc: GICv3 ITS initial framework

[shashi.mallela@linaro.org]

On Mon, 2021-07-05 at 17:25 +0100, Peter Maydell wrote:
> On Mon, 5 Jul 2021 at 16:55, <shashi.mallela@linaro.org> wrote:
> > On Mon, 2021-07-05 at 15:58 +0100, Peter Maydell wrote:
> > > On Wed, 30 Jun 2021 at 16:32, Shashi Mallela <
> > > shashi.mallela@linaro.org> wrote:
> > > > Added register definitions relevant to ITS,implemented overall
> > > > ITS device framework with stubs for ITS control and translater
> > > > regions read/write,extended ITS common to handle mmio init
> > > > between
> > > > existing kvm device and newer qemu device.
> > > > 
> > > > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> > > > +static void gicv3_arm_its_realize(DeviceState *dev, Error
> > > > **errp)
> > > > +{
> > > > +    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
> > > > +
> > > > +    gicv3_its_init_mmio(s, &gicv3_its_control_ops,
> > > > &gicv3_its_translation_ops);
> > > > +
> > > > +    if (s->gicv3->cpu->gicr_typer & GICR_TYPER_PLPIS) {
> > > 
> > > Can you remind me why we make this check, please? When would we
> > > have created an ITS device but not have a GICv3 with LPI support?
> > This check applies to GIC's physical LPI support only as against
> > GIC's
> > virtual LPI support.
> 
> Right, but when would we have a GIC with no physical LPI support
> but an ITS is present ?
If we only support Direct injection of virtual interrupts (which can
have their own vPEID and the vPE table),then the ITS present could havejust virtual LPI support 
> 
> thanks
> -- PMM