From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Eads, Gage" Subject: Re: [PATCH 25/33] app/testeventdev: perf queue: add worker functions Date: Thu, 1 Jun 2017 21:04:15 +0000 Message-ID: <9184057F7FC11744A2107296B6B8EB1E01EC6753@FMSMSX108.amr.corp.intel.com> References: <20170528195854.6064-1-jerin.jacob@caviumnetworks.com> <20170528195854.6064-26-jerin.jacob@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "Richardson, Bruce" , "Van Haaren, Harry" , "hemant.agrawal@nxp.com" , "nipun.gupta@nxp.com" , "Vangati, Narender" , "Rao, Nikhil" , "gprathyusha@caviumnetworks.com" To: Jerin Jacob , "dev@dpdk.org" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 108A07CE4 for ; Thu, 1 Jun 2017 23:04:17 +0200 (CEST) In-Reply-To: <20170528195854.6064-26-jerin.jacob@caviumnetworks.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Sunday, May 28, 2017 2:59 PM > To: dev@dpdk.org > Cc: Richardson, Bruce ; Van Haaren, Harry > ; hemant.agrawal@nxp.com; Eads, Gage > ; nipun.gupta@nxp.com; Vangati, Narender > ; Rao, Nikhil ; > gprathyusha@caviumnetworks.com; Jerin Jacob > > Subject: [dpdk-dev] [PATCH 25/33] app/testeventdev: perf queue: add work= er > functions > =20 > Signed-off-by: Jerin Jacob > --- > app/test-eventdev/test_perf_common.h | 60 +++++++++++++++ app/test- > eventdev/test_perf_queue.c | 137 +++++++++++++++++++++++++++++++++++ > 2 files changed, 197 insertions(+) > =20 > diff --git a/app/test-eventdev/test_perf_common.h b/app/test- > eventdev/test_perf_common.h > index f8246953a..9888e5078 100644 > --- a/app/test-eventdev/test_perf_common.h > +++ b/app/test-eventdev/test_perf_common.h > @@ -86,6 +86,66 @@ struct perf_elt { > uint64_t timestamp; > } __rte_cache_aligned; > =20 > +#define BURST_SIZE 16 > + > +#define PERF_WORKER_INIT\ > + struct worker_data *w =3D arg;\ > + struct test_perf *t =3D w->t;\ > + struct evt_options *opt =3D t->opt;\ > + const uint8_t dev =3D w->dev_id;\ > + const uint8_t port =3D w->port_id;\ > + uint8_t *const sched_type_list =3D &t->sched_type_list[0];\ > + struct rte_mempool *const pool =3D t->pool;\ > + const uint8_t nb_stages =3D t->opt->nb_stages;\ > + const uint8_t laststage =3D nb_stages - 1;\ > + uint8_t cnt =3D 0;\ > + void *bufs[16] __rte_cache_aligned;\ > + int const sz =3D RTE_DIM(bufs);\ > + if (opt->verbose_level > 1)\ > + printf("%s(): lcore %d dev_id %d port=3D%d\n", __func__,\ > + rte_lcore_id(), dev, port) > + > +static inline __attribute__((always_inline)) int > +perf_process_last_stage(struct rte_mempool *const pool, > + struct rte_event *const ev, struct worker_data *const w, > + void *bufs[], int const buf_sz, uint8_t count) { > + bufs[count++] =3D ev->event_ptr; > + w->processed_pkts++; > + rte_smp_wmb(); > + > + if (unlikely(count =3D=3D buf_sz)) { > + count =3D 0; > + rte_mempool_put_bulk(pool, bufs, buf_sz); > + } > + return count; > +} > + > +static inline __attribute__((always_inline)) uint8_t > +perf_process_last_stage_latency(struct rte_mempool *const pool, > + struct rte_event *const ev, struct worker_data *const w, > + void *bufs[], int const buf_sz, uint8_t count) { > + uint64_t latency; > + struct perf_elt *const m =3D ev->event_ptr; > + > + bufs[count++] =3D ev->event_ptr; > + w->processed_pkts++; > + > + if (unlikely(count =3D=3D buf_sz)) { > + count =3D 0; > + latency =3D rte_get_timer_cycles() - m->timestamp; > + rte_mempool_put_bulk(pool, bufs, buf_sz); > + } else { > + latency =3D rte_get_timer_cycles() - m->timestamp; > + } > + > + w->latency +=3D latency; > + rte_smp_wmb(); > + return count; > +} What purpose does the store barrier serve in these two functions?