From: Felix Fietkau <nbd@nbd.name>
To: "Thibaut VARÈNE" <hacks+kernel@slashdirt.org>,
"Toke Høiland-Jørgensen" <toke@toke.dk>,
"Kalle Valo" <kvalo@kernel.org>,
linux-wireless@vger.kernel.org
Cc: "Petr Štetiar" <ynezz@true.cz>, "Clemens Hopfer" <openwrt@wireloss.net>
Subject: Re: [PATCH] ath9k: fix QCA9561 PA bias
Date: Sat, 16 Apr 2022 20:39:33 +0200 [thread overview]
Message-ID: <91c58969-c60e-2f41-00ac-737786d435ae@nbd.name> (raw)
In-Reply-To: <20220415104419.22749-1-hacks+kernel@slashdirt.org>
On 15.04.22 12:44, Thibaut VARÈNE wrote:
> ath9k is setting the TX PA DC bias level differently on QCA9561 and
> QCA9565 although they have the same radio IP-core, which results in a
> very low output power and very low throughput as devices are further
> away from the AP (compared to other 2.4GHz APs).
>
> In real life testing, without this patch the 2.4GHz throughput on
> Yuncore XD3200 is around 10Mbps sitting next to the AP, and close to
> practical maximum with the patch applied.
>
> Tested-by: Petr Štetiar <ynezz@true.cz>
> Signed-off-by: Clemens Hopfer <openwrt@wireloss.net>
> Signed-off-by: Thibaut VARÈNE <hacks+kernel@slashdirt.org>
> ---
> drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
> index b0a4ca355..8f8682f25 100644
> --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
> +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
> @@ -3606,9 +3606,10 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
> int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
>
> if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
> - AR_SREV_9531(ah) || AR_SREV_9561(ah))
> + AR_SREV_9531(ah))
> REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
> - else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))
> + else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9561(ah) ||
> + AR_SREV_9565(ah))
> REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
The patch looks wrong to me. I'm pretty sure that AR_CH0_TOP2 is the
correct register, the definition has an explicit check for 9561 as well.
I believe this patch works by accident because it avoids writing a wrong
value to that register.
The value written to that register is wrong, because while the mask
definition AR_CH0_TOP2_XPABIASLVL uses a different value for 9561, the
shift definition AR_CH0_TOP2_XPABIASLVL_S is hardcoded to 12, which is
wrong for 9561.
Please try adjusting it to this:
#define AR_CH0_TOP2_XPABIASLVL_S (AR_SREV_9561(ah) ? 9 : 12)
- Felix
next prev parent reply other threads:[~2022-04-16 18:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-15 10:44 [PATCH] ath9k: fix QCA9561 PA bias Thibaut VARÈNE
2022-04-16 18:39 ` Felix Fietkau [this message]
2022-04-17 14:46 ` Thibaut VARÈNE
2022-04-17 14:51 ` [PATCH v2] ath9k: fix QCA9561 PA bias level Thibaut VARÈNE
2022-04-17 17:02 ` Felix Fietkau
2022-04-17 19:00 ` Toke Høiland-Jørgensen
2022-04-23 9:32 ` Kalle Valo
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