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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id w3sm17821048wrr.62.2021.02.16.08.48.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Feb 2021 08:48:31 -0800 (PST) To: Joerg Roedel Cc: Peter Zijlstra , Andi Kleen , David Rientjes , Borislav Petkov , Andy Lutomirski , Sean Christopherson , Andrew Morton , "Kirill A. Shutemov" , Brijesh Singh , Tom Lendacky , Jon Grimm , Thomas Gleixner , Christoph Hellwig , Ingo Molnar , x86@kernel.org, linux-mm@kvack.org References: <20210212145318.GK5453@suse.de> <20210212152813.GA28884@suse.de> <20210212161849.GB28884@suse.de> <20210216100045.GE28884@suse.de> <20210216142741.GI365765@tassilo.jf.intel.com> <5ff9690f-331a-8322-3431-212b14f64fcc@redhat.com> <20210216162504.GH12716@suse.de> From: Paolo Bonzini Subject: Re: AMD SEV-SNP/Intel TDX: validation of memory pages Message-ID: <92003e9a-c532-bede-1200-ef3b8f50bc6e@redhat.com> Date: Tue, 16 Feb 2021 17:48:29 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <20210216162504.GH12716@suse.de> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: On 16/02/21 17:25, Joerg Roedel wrote: > On Tue, Feb 16, 2021 at 04:59:52PM +0100, Paolo Bonzini wrote: >> - the inner handler does nothing but telling the outer handler to reru= n. >> The way it does it is certainly not pretty, because it has to work at = any >> instruction boundary, but at its heart it's basically a do{}while loop= . >=20 > That only works if processing of all inner #VE can be deferred, which i= s > not the case for instruction emulation #VEs like MSR accesses, io-port > or MMIO accesses. No doubt about that, but that's unrelated to ISTs. ISTs are ugly and=20 the ugliness is a symptom of the problem; but not part of the problem.=20 NMIs are as usual the most worrisome since you can get those from random=20 perf events. We should minimize the number of #VEs that we get, as they are very=20 slow. Could almost everything that can invoke a #VE go through pvops=20 and be turned into a TDCALL? And if so the same should be true for=20 SEV-ES #VC as well. > I guess those could all be replaced direct TDCALLs, > but the question remains whether this is possible with MSR accesses, me= ans > that the list of MSRs which will cause #VEs is statically defined and > doesn't change between hypervisors. All in all this sounds hard to > maintain and easy to break by unrelated changes. I would expect that all MSRs except for a handful (SPEC_CTRL/PRED_CMD,=20 the FS/GS/kernelGS bases, anything else?) would be redirect to TDCALL. Paolo