[PATCH v2 0/2] riscv: improve unaligned memory accesses

[PATCH v2 0/2] riscv: improve unaligned memory accesses

[Chen Huang]

The patchset improves RISCV unaligned memory accesses, selects
HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
of unaligned memory accesses.

If CPU don't support unaligned memory accesses for now, please
select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
don't support unaligned memory accesses, I don't choose the
CONFIG for them.

Changes since v1:
 - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
   unaligned memory accesses, add an option for CPUs to choose it or not.

Chen Huang (2):
  riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
  riscv: Support DCACHE_WORD_ACCESS

 arch/riscv/Kconfig                      |  5 ++++
 arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

-- 
2.25.1

[PATCH v2 0/2] riscv: improve unaligned memory accesses

[Chen Huang]

The patchset improves RISCV unaligned memory accesses, selects
HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
of unaligned memory accesses.

If CPU don't support unaligned memory accesses for now, please
select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
don't support unaligned memory accesses, I don't choose the
CONFIG for them.

Changes since v1:
 - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
   unaligned memory accesses, add an option for CPUs to choose it or not.

Chen Huang (2):
  riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
  riscv: Support DCACHE_WORD_ACCESS

 arch/riscv/Kconfig                      |  5 ++++
 arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

-- 
2.25.1


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[PATCH v2 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS

[Chen Huang]

This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS. But the feature
maybe not be implemented on some CPUs, or with inefficent
implementation. So add a config CPU_HAS_NO_UNALIGNED, if the CPU
don't want it, please select it.

Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aac669a6c3d8..cd0be39d4c08 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -81,6 +81,7 @@ config RISCV
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DMA_CONTIGUOUS if MMU
 	select HAVE_EBPF_JIT if MMU
+	select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED && MMU
 	select HAVE_FUNCTION_ERROR_INJECTION
 	select HAVE_FUTEX_CMPXCHG if FUTEX
 	select HAVE_GCC_PLUGINS
@@ -382,6 +383,9 @@ config FPU
 
 	  If you don't know what to do here, say Y.
 
+config CPU_HAS_NO_UNALIGNED
+	bool
+
 endmenu
 
 menu "Kernel features"
-- 
2.25.1

[PATCH v2 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS

[Chen Huang]

This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS. But the feature
maybe not be implemented on some CPUs, or with inefficent
implementation. So add a config CPU_HAS_NO_UNALIGNED, if the CPU
don't want it, please select it.

Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aac669a6c3d8..cd0be39d4c08 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -81,6 +81,7 @@ config RISCV
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DMA_CONTIGUOUS if MMU
 	select HAVE_EBPF_JIT if MMU
+	select HAVE_EFFICIENT_UNALIGNED_ACCESS if !CPU_HAS_NO_UNALIGNED && MMU
 	select HAVE_FUNCTION_ERROR_INJECTION
 	select HAVE_FUTEX_CMPXCHG if FUTEX
 	select HAVE_GCC_PLUGINS
@@ -382,6 +383,9 @@ config FPU
 
 	  If you don't know what to do here, say Y.
 
+config CPU_HAS_NO_UNALIGNED
+	bool
+
 endmenu
 
 menu "Kernel features"
-- 
2.25.1


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[PATCH v2 2/2] riscv: Support DCACHE_WORD_ACCESS

[Chen Huang]

This patch selects DCACHE_WORD_ACCESS on riscv and implements support
for load_unaligned_zeropad.

DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string
comparisons in the vfs layer.

Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig                      |  1 +
 arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index cd0be39d4c08..4e98ff76977f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV
 	select CLONE_BACKWARDS
 	select CLINT_TIMER if !MMU
 	select COMMON_CLK
+	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
 	select EDAC_SUPPORT
 	select GENERIC_ARCH_TOPOLOGY if SMP
 	select GENERIC_ATOMIC64 if !64BIT
diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h
index 7c086ac6ecd4..8f4ad1ec39fb 100644
--- a/arch/riscv/include/asm/word-at-a-time.h
+++ b/arch/riscv/include/asm/word-at-a-time.h
@@ -45,4 +45,41 @@ static inline unsigned long find_zero(unsigned long mask)
 /* The mask we created is directly usable as a bytemask */
 #define zero_bytemask(mask) (mask)
 
+#ifdef CONFIG_DCACHE_WORD_ACCESS
+#include <asm/asm.h>
+
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+	unsigned long ret, tmp;
+
+	/* Load word from unaligned pointer addr */
+	asm(
+	"1:	" REG_L " %0, %3\n"
+	"2:\n"
+	"	.section .fixup,\"ax\"\n"
+	"	.balign 2\n"
+	"3:	andi	%1, %2, ~0x7\n"
+	"	" REG_L " %0, (%1)\n"
+	"	andi	%1, %2, 0x7\n"
+	"	slli	%1, %1, 0x3\n"
+	"	srl	%0, %0, %1\n"
+	"	jump	2b, %1\n"
+	"	.previous\n"
+	"	.section __ex_table,\"a\"\n"
+	"	.balign	" RISCV_SZPTR "\n"
+	"	" RISCV_PTR "	1b, 3b\n"
+	"	.previous"
+	: "=&r" (ret), "=&r" (tmp)
+	: "r" (addr), "m" (*(unsigned long *)addr));
+
+	return ret;
+}
+#endif	/* DCACHE_WORD_ACCESS */
 #endif /* _ASM_RISCV_WORD_AT_A_TIME_H */
-- 
2.25.1

[PATCH v2 2/2] riscv: Support DCACHE_WORD_ACCESS

[Chen Huang]

This patch selects DCACHE_WORD_ACCESS on riscv and implements support
for load_unaligned_zeropad.

DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string
comparisons in the vfs layer.

Signed-off-by: Chen Huang <chenhuang5@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
 arch/riscv/Kconfig                      |  1 +
 arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index cd0be39d4c08..4e98ff76977f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -44,6 +44,7 @@ config RISCV
 	select CLONE_BACKWARDS
 	select CLINT_TIMER if !MMU
 	select COMMON_CLK
+	select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
 	select EDAC_SUPPORT
 	select GENERIC_ARCH_TOPOLOGY if SMP
 	select GENERIC_ATOMIC64 if !64BIT
diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/asm/word-at-a-time.h
index 7c086ac6ecd4..8f4ad1ec39fb 100644
--- a/arch/riscv/include/asm/word-at-a-time.h
+++ b/arch/riscv/include/asm/word-at-a-time.h
@@ -45,4 +45,41 @@ static inline unsigned long find_zero(unsigned long mask)
 /* The mask we created is directly usable as a bytemask */
 #define zero_bytemask(mask) (mask)
 
+#ifdef CONFIG_DCACHE_WORD_ACCESS
+#include <asm/asm.h>
+
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+	unsigned long ret, tmp;
+
+	/* Load word from unaligned pointer addr */
+	asm(
+	"1:	" REG_L " %0, %3\n"
+	"2:\n"
+	"	.section .fixup,\"ax\"\n"
+	"	.balign 2\n"
+	"3:	andi	%1, %2, ~0x7\n"
+	"	" REG_L " %0, (%1)\n"
+	"	andi	%1, %2, 0x7\n"
+	"	slli	%1, %1, 0x3\n"
+	"	srl	%0, %0, %1\n"
+	"	jump	2b, %1\n"
+	"	.previous\n"
+	"	.section __ex_table,\"a\"\n"
+	"	.balign	" RISCV_SZPTR "\n"
+	"	" RISCV_PTR "	1b, 3b\n"
+	"	.previous"
+	: "=&r" (ret), "=&r" (tmp)
+	: "r" (addr), "m" (*(unsigned long *)addr));
+
+	return ret;
+}
+#endif	/* DCACHE_WORD_ACCESS */
 #endif /* _ASM_RISCV_WORD_AT_A_TIME_H */
-- 
2.25.1


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Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Jisheng Zhang]

On Thu, 16 Sep 2021 13:08:53 +0000
Chen Huang <chenhuang5@huawei.com> wrote:

> The patchset improves RISCV unaligned memory accesses, selects
> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
> of unaligned memory accesses.
> 
> If CPU don't support unaligned memory accesses for now, please
> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
> don't support unaligned memory accesses, I don't choose the
> CONFIG for them.

This will break unified kernel Image for riscv. Obviously, we will have
two images for efficient unaligned access platforms and non-efficient
unaligned access platforms. IMHO, we may need alternative mechanism or
something else to dynamically enable related code path.

Regards

> 
> Changes since v1:
>  - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>    unaligned memory accesses, add an option for CPUs to choose it or not.
> 
> Chen Huang (2):
>   riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>   riscv: Support DCACHE_WORD_ACCESS
> 
>  arch/riscv/Kconfig                      |  5 ++++
>  arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>  2 files changed, 42 insertions(+)
> 

Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Jisheng Zhang]

On Thu, 16 Sep 2021 13:08:53 +0000
Chen Huang <chenhuang5@huawei.com> wrote:

> The patchset improves RISCV unaligned memory accesses, selects
> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
> of unaligned memory accesses.
> 
> If CPU don't support unaligned memory accesses for now, please
> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
> don't support unaligned memory accesses, I don't choose the
> CONFIG for them.

This will break unified kernel Image for riscv. Obviously, we will have
two images for efficient unaligned access platforms and non-efficient
unaligned access platforms. IMHO, we may need alternative mechanism or
something else to dynamically enable related code path.

Regards

> 
> Changes since v1:
>  - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>    unaligned memory accesses, add an option for CPUs to choose it or not.
> 
> Chen Huang (2):
>   riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>   riscv: Support DCACHE_WORD_ACCESS
> 
>  arch/riscv/Kconfig                      |  5 ++++
>  arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>  2 files changed, 42 insertions(+)
> 



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Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Kefeng Wang]

On 2021/9/17 22:14, Jisheng Zhang wrote:
> On Thu, 16 Sep 2021 13:08:53 +0000
> Chen Huang <chenhuang5@huawei.com> wrote:
>
>> The patchset improves RISCV unaligned memory accesses, selects
>> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
>> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
>> of unaligned memory accesses.
>>
>> If CPU don't support unaligned memory accesses for now, please
>> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
>> don't support unaligned memory accesses, I don't choose the
>> CONFIG for them.
> This will break unified kernel Image for riscv. Obviously, we will have
> two images for efficient unaligned access platforms and non-efficient
> unaligned access platforms. IMHO, we may need alternative mechanism or
> something else to dynamically enable related code path.

it won't break unified kernel Image for riscv, if one SoC choose

CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory

accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has

similar configuration.

Yes,  it could be an optimization via alternative mechanism or something 
else to

dynamically enable related code path later.

>
> Regards
>
>> Changes since v1:
>>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>>     unaligned memory accesses, add an option for CPUs to choose it or not.
>>
>> Chen Huang (2):
>>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>>    riscv: Support DCACHE_WORD_ACCESS
>>
>>   arch/riscv/Kconfig                      |  5 ++++
>>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>>   2 files changed, 42 insertions(+)
>>
>
> .
>

Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Kefeng Wang]

On 2021/9/17 22:14, Jisheng Zhang wrote:
> On Thu, 16 Sep 2021 13:08:53 +0000
> Chen Huang <chenhuang5@huawei.com> wrote:
>
>> The patchset improves RISCV unaligned memory accesses, selects
>> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
>> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
>> of unaligned memory accesses.
>>
>> If CPU don't support unaligned memory accesses for now, please
>> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
>> don't support unaligned memory accesses, I don't choose the
>> CONFIG for them.
> This will break unified kernel Image for riscv. Obviously, we will have
> two images for efficient unaligned access platforms and non-efficient
> unaligned access platforms. IMHO, we may need alternative mechanism or
> something else to dynamically enable related code path.

it won't break unified kernel Image for riscv, if one SoC choose

CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory

accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has

similar configuration.

Yes,  it could be an optimization via alternative mechanism or something 
else to

dynamically enable related code path later.

>
> Regards
>
>> Changes since v1:
>>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>>     unaligned memory accesses, add an option for CPUs to choose it or not.
>>
>> Chen Huang (2):
>>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>>    riscv: Support DCACHE_WORD_ACCESS
>>
>>   arch/riscv/Kconfig                      |  5 ++++
>>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>>   2 files changed, 42 insertions(+)
>>
>
> .
>

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Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Jisheng Zhang]

On Sat, 18 Sep 2021 09:14:05 +0800
Kefeng Wang <wangkefeng.wang@huawei.com> wrote:

> On 2021/9/17 22:14, Jisheng Zhang wrote:
> > On Thu, 16 Sep 2021 13:08:53 +0000
> > Chen Huang <chenhuang5@huawei.com> wrote:
> >  
> >> The patchset improves RISCV unaligned memory accesses, selects
> >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
> >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
> >> of unaligned memory accesses.
> >>
> >> If CPU don't support unaligned memory accesses for now, please
> >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
> >> don't support unaligned memory accesses, I don't choose the
> >> CONFIG for them.  
> > This will break unified kernel Image for riscv. Obviously, we will have
> > two images for efficient unaligned access platforms and non-efficient
> > unaligned access platforms. IMHO, we may need alternative mechanism or
> > something else to dynamically enable related code path.  
> 
> it won't break unified kernel Image for riscv, if one SoC choose
> 
> CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory

the "unified" means the kernel Image has to support all RV64GC or RV32GC SoCs.
To make the Image works for both efficient unaligned access and inefficient
unaligned access, I think we'd better make "inefficient unaligned access"
default behavior, the use alternative etc. tech to patch related code path
for efficient unaligned access.


> 
> accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has

linux Distributions doesn't have enough background of which config options
must be enabled.

> 
> similar configuration.

I have little knowledge of powerpc or m68k, but there are serveral different
defconfig files for arm, for example multi_v7_defconfig and multi_v5_defconfig.
The previous v7 version enables HAVE_EFFICIENT_UNALIGNED_ACCESS while
the later v5 doesn't. Will you persuade riscv maintainers to accept one more
defconfig file?

Thanks

> 
> Yes,  it could be an optimization via alternative mechanism or something 
> else to
> 
> dynamically enable related code path later.
> 
> >
> > Regards
> >  
> >> Changes since v1:
> >>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
> >>     unaligned memory accesses, add an option for CPUs to choose it or not.
> >>
> >> Chen Huang (2):
> >>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
> >>    riscv: Support DCACHE_WORD_ACCESS
> >>
> >>   arch/riscv/Kconfig                      |  5 ++++
> >>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
> >>   2 files changed, 42 insertions(+)
> >>  
> >
> > .
> >  

Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Jisheng Zhang]

On Sat, 18 Sep 2021 09:14:05 +0800
Kefeng Wang <wangkefeng.wang@huawei.com> wrote:

> On 2021/9/17 22:14, Jisheng Zhang wrote:
> > On Thu, 16 Sep 2021 13:08:53 +0000
> > Chen Huang <chenhuang5@huawei.com> wrote:
> >  
> >> The patchset improves RISCV unaligned memory accesses, selects
> >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
> >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
> >> of unaligned memory accesses.
> >>
> >> If CPU don't support unaligned memory accesses for now, please
> >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
> >> don't support unaligned memory accesses, I don't choose the
> >> CONFIG for them.  
> > This will break unified kernel Image for riscv. Obviously, we will have
> > two images for efficient unaligned access platforms and non-efficient
> > unaligned access platforms. IMHO, we may need alternative mechanism or
> > something else to dynamically enable related code path.  
> 
> it won't break unified kernel Image for riscv, if one SoC choose
> 
> CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory

the "unified" means the kernel Image has to support all RV64GC or RV32GC SoCs.
To make the Image works for both efficient unaligned access and inefficient
unaligned access, I think we'd better make "inefficient unaligned access"
default behavior, the use alternative etc. tech to patch related code path
for efficient unaligned access.


> 
> accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has

linux Distributions doesn't have enough background of which config options
must be enabled.

> 
> similar configuration.

I have little knowledge of powerpc or m68k, but there are serveral different
defconfig files for arm, for example multi_v7_defconfig and multi_v5_defconfig.
The previous v7 version enables HAVE_EFFICIENT_UNALIGNED_ACCESS while
the later v5 doesn't. Will you persuade riscv maintainers to accept one more
defconfig file?

Thanks

> 
> Yes,  it could be an optimization via alternative mechanism or something 
> else to
> 
> dynamically enable related code path later.
> 
> >
> > Regards
> >  
> >> Changes since v1:
> >>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
> >>     unaligned memory accesses, add an option for CPUs to choose it or not.
> >>
> >> Chen Huang (2):
> >>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
> >>    riscv: Support DCACHE_WORD_ACCESS
> >>
> >>   arch/riscv/Kconfig                      |  5 ++++
> >>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
> >>   2 files changed, 42 insertions(+)
> >>  
> >
> > .
> >  



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Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Palmer Dabbelt]

On Sat, 18 Sep 2021 07:17:13 PDT (-0700), jszhang3@mail.ustc.edu.cn wrote:
> On Sat, 18 Sep 2021 09:14:05 +0800
> Kefeng Wang <wangkefeng.wang@huawei.com> wrote:
>
>> On 2021/9/17 22:14, Jisheng Zhang wrote:
>> > On Thu, 16 Sep 2021 13:08:53 +0000
>> > Chen Huang <chenhuang5@huawei.com> wrote:
>> >  
>> >> The patchset improves RISCV unaligned memory accesses, selects
>> >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
>> >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
>> >> of unaligned memory accesses.
>> >>
>> >> If CPU don't support unaligned memory accesses for now, please
>> >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
>> >> don't support unaligned memory accesses, I don't choose the
>> >> CONFIG for them.  
>> > This will break unified kernel Image for riscv. Obviously, we will have
>> > two images for efficient unaligned access platforms and non-efficient
>> > unaligned access platforms. IMHO, we may need alternative mechanism or
>> > something else to dynamically enable related code path.  
>> 
>> it won't break unified kernel Image for riscv, if one SoC choose
>> 
>> CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory
>
> the "unified" means the kernel Image has to support all RV64GC or RV32GC SoCs.
> To make the Image works for both efficient unaligned access and inefficient
> unaligned access, I think we'd better make "inefficient unaligned access"
> default behavior, the use alternative etc. tech to patch related code path
> for efficient unaligned access.

I agree, at least until we have a sufficient breadth of implementations 
to know whether efficient unaligned accesses are going to be possible.

There was also a question about what exactly the C906 unaligned access 
handling looks like on GCC, as well.  Do you guys have any sort of 
pipeline description?

>
>
>> 
>> accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has
>
> linux Distributions doesn't have enough background of which config options
> must be enabled.

I wouldn't be opposed to adding this as a Kconfig option, something 
along the lines of "tune for fast unaligned accesses" or whatever.  I 
get that we're sort of just punting the problem to distros, but we could 
add a Kconfig.socs-like (though that is a mess, so we'd need something 
saner) tune target (which is maybe coupled to -mtune, as well?).  That 
would a least let us give users the option of making this choice, and 
while it'd still likely be best to set this to slow unaligned accesse to 
start we may be able to more easily see what distros choose at this 
point.

>
>> 
>> similar configuration.
>
> I have little knowledge of powerpc or m68k, but there are serveral different
> defconfig files for arm, for example multi_v7_defconfig and multi_v5_defconfig.
> The previous v7 version enables HAVE_EFFICIENT_UNALIGNED_ACCESS while
> the later v5 doesn't. Will you persuade riscv maintainers to accept one more
> defconfig file?

I'm not super worried about having more defconfigs, but I'm not really 
sure it's worth it for this option alone.

>
> Thanks
>
>> 
>> Yes,  it could be an optimization via alternative mechanism or something 
>> else to
>> 
>> dynamically enable related code path later.
>> 
>> >
>> > Regards
>> >  
>> >> Changes since v1:
>> >>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>> >>     unaligned memory accesses, add an option for CPUs to choose it or not.
>> >>
>> >> Chen Huang (2):
>> >>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>> >>    riscv: Support DCACHE_WORD_ACCESS
>> >>
>> >>   arch/riscv/Kconfig                      |  5 ++++
>> >>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>> >>   2 files changed, 42 insertions(+)
>> >>  
>> >
>> > .
>> >  

Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Palmer Dabbelt]

On Sat, 18 Sep 2021 07:17:13 PDT (-0700), jszhang3@mail.ustc.edu.cn wrote:
> On Sat, 18 Sep 2021 09:14:05 +0800
> Kefeng Wang <wangkefeng.wang@huawei.com> wrote:
>
>> On 2021/9/17 22:14, Jisheng Zhang wrote:
>> > On Thu, 16 Sep 2021 13:08:53 +0000
>> > Chen Huang <chenhuang5@huawei.com> wrote:
>> >  
>> >> The patchset improves RISCV unaligned memory accesses, selects
>> >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
>> >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
>> >> of unaligned memory accesses.
>> >>
>> >> If CPU don't support unaligned memory accesses for now, please
>> >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
>> >> don't support unaligned memory accesses, I don't choose the
>> >> CONFIG for them.  
>> > This will break unified kernel Image for riscv. Obviously, we will have
>> > two images for efficient unaligned access platforms and non-efficient
>> > unaligned access platforms. IMHO, we may need alternative mechanism or
>> > something else to dynamically enable related code path.  
>> 
>> it won't break unified kernel Image for riscv, if one SoC choose
>> 
>> CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory
>
> the "unified" means the kernel Image has to support all RV64GC or RV32GC SoCs.
> To make the Image works for both efficient unaligned access and inefficient
> unaligned access, I think we'd better make "inefficient unaligned access"
> default behavior, the use alternative etc. tech to patch related code path
> for efficient unaligned access.

I agree, at least until we have a sufficient breadth of implementations 
to know whether efficient unaligned accesses are going to be possible.

There was also a question about what exactly the C906 unaligned access 
handling looks like on GCC, as well.  Do you guys have any sort of 
pipeline description?

>
>
>> 
>> accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has
>
> linux Distributions doesn't have enough background of which config options
> must be enabled.

I wouldn't be opposed to adding this as a Kconfig option, something 
along the lines of "tune for fast unaligned accesses" or whatever.  I 
get that we're sort of just punting the problem to distros, but we could 
add a Kconfig.socs-like (though that is a mess, so we'd need something 
saner) tune target (which is maybe coupled to -mtune, as well?).  That 
would a least let us give users the option of making this choice, and 
while it'd still likely be best to set this to slow unaligned accesse to 
start we may be able to more easily see what distros choose at this 
point.

>
>> 
>> similar configuration.
>
> I have little knowledge of powerpc or m68k, but there are serveral different
> defconfig files for arm, for example multi_v7_defconfig and multi_v5_defconfig.
> The previous v7 version enables HAVE_EFFICIENT_UNALIGNED_ACCESS while
> the later v5 doesn't. Will you persuade riscv maintainers to accept one more
> defconfig file?

I'm not super worried about having more defconfigs, but I'm not really 
sure it's worth it for this option alone.

>
> Thanks
>
>> 
>> Yes,  it could be an optimization via alternative mechanism or something 
>> else to
>> 
>> dynamically enable related code path later.
>> 
>> >
>> > Regards
>> >  
>> >> Changes since v1:
>> >>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>> >>     unaligned memory accesses, add an option for CPUs to choose it or not.
>> >>
>> >> Chen Huang (2):
>> >>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>> >>    riscv: Support DCACHE_WORD_ACCESS
>> >>
>> >>   arch/riscv/Kconfig                      |  5 ++++
>> >>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>> >>   2 files changed, 42 insertions(+)
>> >>  
>> >
>> > .
>> >  

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