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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 08:41:02.7086 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc49b2fa-9d1c-4e92-8de3-08db3cc3fad6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT007.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9744 Hi Luca, > On 12 Apr 2023, at 11:49, Luca Fancellu wrote: >=20 > SVE has a new exception class with code 0x19, introduce the new code > and handle the exception. >=20 > Signed-off-by: Luca Fancellu With the comments from Julien handled you can add my: Reviewed-by: Bertrand Marquis Cheers Bertrand > --- > Changes from v4: > - No changes > Changes from v3: > - No changes > Changes from v2: > - No changes > Changes from v1: > - No changes > Changes from RFC: > - No changes > --- > xen/arch/arm/include/asm/processor.h | 1 + > xen/arch/arm/traps.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) >=20 > diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/= asm/processor.h > index bc683334125c..7e42ff8811fc 100644 > --- a/xen/arch/arm/include/asm/processor.h > +++ b/xen/arch/arm/include/asm/processor.h > @@ -426,6 +426,7 @@ > #define HSR_EC_HVC64 0x16 > #define HSR_EC_SMC64 0x17 > #define HSR_EC_SYSREG 0x18 > +#define HSR_EC_SVE 0x19 > #endif > #define HSR_EC_INSTR_ABORT_LOWER_EL 0x20 > #define HSR_EC_INSTR_ABORT_CURR_EL 0x21 > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index a78a99ddadd0..c2e30feafd5a 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -2160,6 +2160,13 @@ void do_trap_guest_sync(struct cpu_user_regs *regs= ) > perfc_incr(trap_sysreg); > do_sysreg(regs, hsr); > break; > + case HSR_EC_SVE: > + GUEST_BUG_ON(regs_mode_is_32bit(regs)); > + gprintk(XENLOG_WARNING, > + "Domain id %d tried to use SVE while not allowed\n", > + current->domain->domain_id); > + inject_undef_exception(regs, hsr); > + break; > #endif >=20 > case HSR_EC_INSTR_ABORT_LOWER_EL: > @@ -2189,6 +2196,11 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs) > case HSR_EC_BRK: > do_trap_brk(regs, hsr); > break; > + case HSR_EC_SVE: > + /* An SVE exception is a bug somewhere in hypervisor code */ > + printk("SVE trap at EL2.\n"); > + do_unexpected_trap("Hypervisor", regs); > + break; > #endif > case HSR_EC_DATA_ABORT_CURR_EL: > case HSR_EC_INSTR_ABORT_CURR_EL: > --=20 > 2.34.1 >=20