From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Patel, Mayurkumar" Subject: RE: [PATCH V8 4/5] PCI/ASPM: save power on values during bridge init Date: Fri, 21 Apr 2017 14:13:42 +0000 Message-ID: <92EBB4272BF81E4089A7126EC1E7B2846676CC01@IRSMSX101.ger.corp.intel.com> References: <1491627351-1111-1-git-send-email-okaya@codeaurora.org> <1491627351-1111-5-git-send-email-okaya@codeaurora.org> <20170414214452.GA21870@bhelgaas-glaptop.roam.corp.google.com> <66168dde-7719-6f74-3f06-8e4724dd2918@codeaurora.org> <92EBB4272BF81E4089A7126EC1E7B2846676C7EF@IRSMSX101.ger.corp.intel.com> <16c80ef9-8928-b7c9-dc6e-f1c96efb6da3@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <16c80ef9-8928-b7c9-dc6e-f1c96efb6da3@codeaurora.org> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Sinan Kaya , Bjorn Helgaas Cc: Rajat Jain , Myron Stowe , David Daney , "linux-pci@vger.kernel.org" , Timur Tabi , "linux-kernel@vger.kernel.org" , Julia Lawall , Bjorn Helgaas , linux-arm-msm , Rajat Jain , Yinghai Lu , Shawn Lin , linux-arm List-Id: linux-arm-msm@vger.kernel.org > >On 4/21/2017 3:46 AM, Patel, Mayurkumar wrote: >> If we want to follow above approach then shall we consider having something similar as following? > >Do you see this problem if you boot with pcie_aspm.policy=powersave option? > No problems. with pcie_aspm.policy=powersave(L1SS are not enabled in this case but L1 stays ok all the time after many Power(hotplug) cycles but I think that is expected with this policy) and pcie_aspm.policy=powersupersave (L1/L1SS both stays ok all the time). > >-- >Sinan Kaya >Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. >Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1040338AbdDUOQT (ORCPT ); Fri, 21 Apr 2017 10:16:19 -0400 Received: from mga02.intel.com ([134.134.136.20]:9826 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1040583AbdDUOOl (ORCPT ); Fri, 21 Apr 2017 10:14:41 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,230,1488873600"; d="scan'208";a="848410413" From: "Patel, Mayurkumar" To: Sinan Kaya , Bjorn Helgaas CC: Bjorn Helgaas , Rajat Jain , "Rajat Jain" , David Daney , "linux-pci@vger.kernel.org" , Timur Tabi , "linux-kernel@vger.kernel.org" , Julia Lawall , linux-arm-msm , Yinghai Lu , Shawn Lin , linux-arm , Myron Stowe Subject: RE: [PATCH V8 4/5] PCI/ASPM: save power on values during bridge init Thread-Topic: [PATCH V8 4/5] PCI/ASPM: save power on values during bridge init Thread-Index: AQHSsCR5lQf5ZNPCu0maCYKOKGfA0KHCEjuAgAMi3oCAACqMAIAACP0AgARYXoCAABQGgIAEPdjQgAHIh4CAABXhQA== Date: Fri, 21 Apr 2017 14:13:42 +0000 Message-ID: <92EBB4272BF81E4089A7126EC1E7B2846676CC01@IRSMSX101.ger.corp.intel.com> References: <1491627351-1111-1-git-send-email-okaya@codeaurora.org> <1491627351-1111-5-git-send-email-okaya@codeaurora.org> <20170414214452.GA21870@bhelgaas-glaptop.roam.corp.google.com> <66168dde-7719-6f74-3f06-8e4724dd2918@codeaurora.org> <92EBB4272BF81E4089A7126EC1E7B2846676C7EF@IRSMSX101.ger.corp.intel.com> <16c80ef9-8928-b7c9-dc6e-f1c96efb6da3@codeaurora.org> In-Reply-To: <16c80ef9-8928-b7c9-dc6e-f1c96efb6da3@codeaurora.org> Accept-Language: de-DE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v3LEGTgZ015462 > >On 4/21/2017 3:46 AM, Patel, Mayurkumar wrote: >> If we want to follow above approach then shall we consider having something similar as following? > >Do you see this problem if you boot with pcie_aspm.policy=powersave option? > No problems. with pcie_aspm.policy=powersave(L1SS are not enabled in this case but L1 stays ok all the time after many Power(hotplug) cycles but I think that is expected with this policy) and pcie_aspm.policy=powersupersave (L1/L1SS both stays ok all the time). > >-- >Sinan Kaya >Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. >Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: "Patel, Mayurkumar" To: Sinan Kaya , Bjorn Helgaas CC: Bjorn Helgaas , Rajat Jain , "Rajat Jain" , David Daney , "linux-pci@vger.kernel.org" , Timur Tabi , "linux-kernel@vger.kernel.org" , Julia Lawall , linux-arm-msm , Yinghai Lu , Shawn Lin , linux-arm , Myron Stowe Subject: RE: [PATCH V8 4/5] PCI/ASPM: save power on values during bridge init Date: Fri, 21 Apr 2017 14:13:42 +0000 Message-ID: <92EBB4272BF81E4089A7126EC1E7B2846676CC01@IRSMSX101.ger.corp.intel.com> References: <1491627351-1111-1-git-send-email-okaya@codeaurora.org> <1491627351-1111-5-git-send-email-okaya@codeaurora.org> <20170414214452.GA21870@bhelgaas-glaptop.roam.corp.google.com> <66168dde-7719-6f74-3f06-8e4724dd2918@codeaurora.org> <92EBB4272BF81E4089A7126EC1E7B2846676C7EF@IRSMSX101.ger.corp.intel.com> <16c80ef9-8928-b7c9-dc6e-f1c96efb6da3@codeaurora.org> In-Reply-To: <16c80ef9-8928-b7c9-dc6e-f1c96efb6da3@codeaurora.org> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 List-ID: Pg0KPk9uIDQvMjEvMjAxNyAzOjQ2IEFNLCBQYXRlbCwgTWF5dXJrdW1hciB3cm90ZToNCj4+IElm IHdlIHdhbnQgdG8gZm9sbG93IGFib3ZlIGFwcHJvYWNoIHRoZW4gc2hhbGwgd2UgY29uc2lkZXIg aGF2aW5nIHNvbWV0aGluZyBzaW1pbGFyIGFzIGZvbGxvd2luZz8NCj4NCj5EbyB5b3Ugc2VlIHRo aXMgcHJvYmxlbSBpZiB5b3UgYm9vdCB3aXRoIHBjaWVfYXNwbS5wb2xpY3k9cG93ZXJzYXZlIG9w dGlvbj8NCj4NCg0KTm8gcHJvYmxlbXMuIHdpdGggcGNpZV9hc3BtLnBvbGljeT1wb3dlcnNhdmUo TDFTUyBhcmUgbm90IGVuYWJsZWQgaW4gdGhpcyBjYXNlDQpidXQgTDEgc3RheXMgb2sgYWxsIHRo ZSB0aW1lIGFmdGVyIG1hbnkgUG93ZXIoaG90cGx1ZykgY3ljbGVzIGJ1dCBJIHRoaW5rIHRoYXQg aXMgZXhwZWN0ZWQgd2l0aCB0aGlzIHBvbGljeSkNCmFuZCBwY2llX2FzcG0ucG9saWN5PXBvd2Vy c3VwZXJzYXZlIChMMS9MMVNTIGJvdGggc3RheXMgb2sgYWxsIHRoZSB0aW1lKS4NCg0KPg0KPi0t DQo+U2luYW4gS2F5YQ0KPlF1YWxjb21tIERhdGFjZW50ZXIgVGVjaG5vbG9naWVzLCBJbmMuIGFz IGFuIGFmZmlsaWF0ZSBvZiBRdWFsY29tbSBUZWNobm9sb2dpZXMsIEluYy4NCj5RdWFsY29tbSBU ZWNobm9sb2dpZXMsIEluYy4gaXMgYSBtZW1iZXIgb2YgdGhlIENvZGUgQXVyb3JhIEZvcnVtLCBh IExpbnV4IEZvdW5kYXRpb24gQ29sbGFib3JhdGl2ZSBQcm9qZWN0Lg0KSW50ZWwgRGV1dHNjaGxh bmQgR21iSApSZWdpc3RlcmVkIEFkZHJlc3M6IEFtIENhbXBlb24gMTAtMTIsIDg1NTc5IE5ldWJp YmVyZywgR2VybWFueQpUZWw6ICs0OSA4OSA5OSA4ODUzLTAsIHd3dy5pbnRlbC5kZQpNYW5hZ2lu ZyBEaXJlY3RvcnM6IENocmlzdGluIEVpc2Vuc2NobWlkLCBDaHJpc3RpYW4gTGFtcHJlY2h0ZXIK Q2hhaXJwZXJzb24gb2YgdGhlIFN1cGVydmlzb3J5IEJvYXJkOiBOaWNvbGUgTGF1ClJlZ2lzdGVy ZWQgT2ZmaWNlOiBNdW5pY2gKQ29tbWVyY2lhbCBSZWdpc3RlcjogQW10c2dlcmljaHQgTXVlbmNo ZW4gSFJCIDE4NjkyOAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: mayurkumar.patel@intel.com (Patel, Mayurkumar) Date: Fri, 21 Apr 2017 14:13:42 +0000 Subject: [PATCH V8 4/5] PCI/ASPM: save power on values during bridge init In-Reply-To: <16c80ef9-8928-b7c9-dc6e-f1c96efb6da3@codeaurora.org> References: <1491627351-1111-1-git-send-email-okaya@codeaurora.org> <1491627351-1111-5-git-send-email-okaya@codeaurora.org> <20170414214452.GA21870@bhelgaas-glaptop.roam.corp.google.com> <66168dde-7719-6f74-3f06-8e4724dd2918@codeaurora.org> <92EBB4272BF81E4089A7126EC1E7B2846676C7EF@IRSMSX101.ger.corp.intel.com> <16c80ef9-8928-b7c9-dc6e-f1c96efb6da3@codeaurora.org> Message-ID: <92EBB4272BF81E4089A7126EC1E7B2846676CC01@IRSMSX101.ger.corp.intel.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > >On 4/21/2017 3:46 AM, Patel, Mayurkumar wrote: >> If we want to follow above approach then shall we consider having something similar as following? > >Do you see this problem if you boot with pcie_aspm.policy=powersave option? > No problems. with pcie_aspm.policy=powersave(L1SS are not enabled in this case but L1 stays ok all the time after many Power(hotplug) cycles but I think that is expected with this policy) and pcie_aspm.policy=powersupersave (L1/L1SS both stays ok all the time). > >-- >Sinan Kaya >Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. >Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. Intel Deutschland GmbH Registered Address: Am Campeon 10-12, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Christian Lamprechter Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928