From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6282FC47082 for ; Thu, 3 Jun 2021 17:00:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4BBB561159 for ; Thu, 3 Jun 2021 17:00:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229695AbhFCRCW (ORCPT ); Thu, 3 Jun 2021 13:02:22 -0400 Received: from mail-pg1-f169.google.com ([209.85.215.169]:35420 "EHLO mail-pg1-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230339AbhFCRCV (ORCPT ); Thu, 3 Jun 2021 13:02:21 -0400 Received: by mail-pg1-f169.google.com with SMTP id o9so2789566pgd.2 for ; Thu, 03 Jun 2021 10:00:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to; bh=ySbi2+Sg+1Js0aJCbxSBMX8t1rC02n924vpr8m+WTTI=; b=C4p+W8SRj0SzjrDYvgpsyO5yaAiAn+0s+7fiC7lzb2aPxw10uum+k4JmKJMp7x9NRk f82w7Sg9Shg6PEycJDrMfWjEWQkpOukhcuVbIFuM8iRirNKQeQOJLM5+CIL923ZxMb2G 3NNfUiddHAre+EmGZVpYjiX6Hm1XYWBLhmh/0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to; bh=ySbi2+Sg+1Js0aJCbxSBMX8t1rC02n924vpr8m+WTTI=; b=uYDVbAM8c2/2/rl5G+sswvd2v6GlVL5YP5RnHVoNPfSazbBUFXa3jBupogTbdurzN3 SK+/One5qVeqNzWuunLcm8GZzfU1Vs9XMWn5DCMr8NOvbtE5nffz4kiSPi1nJA2ZCHKH 59eblX+Xx807v1AjD6mObD1iFIlZ2Gr6zpdoVQN/kF8kHDN4cb9ckVCLMc5e2byHmw/E 52IcmKCV62JkhUPb6dl7TYYA5wLlulkbzIoKAIlRIOaqN/2BU8EjJkcRirxMeyOvsSAn kxxMhYTbfW/Eonkt8tjkojVgzwzFKpKa8eKIk/fqs7nreRb86au/oGlFYtuGX8Zizje4 ylbw== X-Gm-Message-State: AOAM533O18M+BFiN47FXqHquDp5Svz2/UWHIGOrYWWmoVRiNRHvOWUcG 5UpzkmUang+qwA8HRVGCRqaR9w== X-Google-Smtp-Source: ABdhPJxCIytBfcv/Za+lgM1Z5e19NnMECWHdOBdZbYth2ENmfGDPOzxL1JNKzKoZZtcfoP4gWUcgrg== X-Received: by 2002:aa7:9216:0:b029:2e5:6989:4f1a with SMTP id 22-20020aa792160000b02902e569894f1amr33599pfo.50.1622739576357; Thu, 03 Jun 2021 09:59:36 -0700 (PDT) Received: from [10.136.8.240] ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id l5sm2739638pff.20.2021.06.03.09.59.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Jun 2021 09:59:35 -0700 (PDT) Subject: Re: pcie-iproc-msi.c: Bug in Multi-MSI support? To: Marc Zyngier , Sandor Bodo-Merle Cc: =?UTF-8?Q?Pali_Roh=c3=a1r?= , linux-pci@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com References: <20210520120055.jl7vkqanv7wzeipq@pali> <20210520140529.rczoz3npjoadzfqc@pali> <4e972ecb-43df-639f-052d-8d1518bae9c0@broadcom.com> <87pmxgwh7o.wl-maz@kernel.org> <13a7e409-646d-40a7-17a0-4e4be011efb2@broadcom.com> <874keqvsf2.wl-maz@kernel.org> <87bl8o1x8c.wl-maz@kernel.org> From: Ray Jui Message-ID: <92a918e6-37cc-8892-a665-4121b3200f00@broadcom.com> Date: Thu, 3 Jun 2021 09:59:33 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <87bl8o1x8c.wl-maz@kernel.org> Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="0000000000000b9d7105c3df802b" Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org --0000000000000b9d7105c3df802b Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit On 6/2/2021 1:34 AM, Marc Zyngier wrote: > On Wed, 26 May 2021 17:10:24 +0100, > Sandor Bodo-Merle wrote: >> >> [1 ] >> The following patch addresses the allocation issue - but indeed - wont >> fix the atomicity of IRQ affinity in this driver (but the majority of >> our product relies on single core SOCs; we also use a dual-core SOC >> also - but we don't change the initial the IRQ affinity). >> >> On Wed, May 26, 2021 at 9:57 AM Marc Zyngier wrote: >>> >>> On Tue, 25 May 2021 18:27:54 +0100, >>> Ray Jui wrote: >>>> >>>> On 5/24/2021 3:37 AM, Marc Zyngier wrote: >>>>> On Thu, 20 May 2021 18:11:32 +0100, >>>>> Ray Jui wrote: >>>>>> >>>>>> On 5/20/2021 7:22 AM, Sandor Bodo-Merle wrote: >>> >>> [...] >>> >>>>>> I guess I'm not too clear on what you mean by "multi-MSI interrupts >>>>>> needs to be aligned to number of requested interrupts.". Would you be >>>>>> able to plug this into the above explanation so we can have a more clear >>>>>> understanding of what you mean here? >>>>> >>>>> That's a generic PCI requirement: if you are providing a Multi-MSI >>>>> configuration, the base vector number has to be size-aligned >>>>> (2-aligned for 2 MSIs, 4 aligned for 4, up to 32), and the end-point >>>>> supplies up to 5 bits that are orr-ed into the base vector number, >>>>> with a *single* doorbell address. You effectively provide a single MSI >>>>> number and a single address, and the device knows how to drive 2^n MSIs. >>>>> >>>>> This is different from MSI-X, which defines multiple individual >>>>> vectors, each with their own doorbell address. >>>>> >>>>> The main problem you have here (other than the broken allocation >>>>> mechanism) is that moving an interrupt from one core to another >>>>> implies moving the doorbell address to that of another MSI >>>>> group. This isn't possible for Multi-MSI, as all the MSIs must have >>>>> the same doorbell address. As far as I can see, there is no way to >>>>> support Multi-MSI together with affinity change on this HW, and you >>>>> should stop advertising support for this feature. >>>>> >>>> >>>> I was not aware of the fact that multi-MSI needs to use the same >>>> doorbell address (aka MSI posted write address?). Thank you for helping >>>> to point it out. In this case, yes, like you said, we cannot possibly >>>> support both multi-MSI and affinity at the same time, since supporting >>>> affinity requires us to move from one to another event queue (and irq) >>>> that will have different doorbell address. >>>> >>>> Do you think it makes sense to do the following by only advertising >>>> multi-MSI capability in the single CPU core case (detected runtime via >>>> 'num_possible_cpus')? This will at least allow multi-MSI to work in >>>> platforms with single CPU core that Sandor and Pali use? >>> >>> I don't think this makes much sense. Single-CPU machines are an oddity >>> these days, and I'd rather you simplify this (already pretty >>> complicated) driver. >>> >>>>> There is also a more general problem here, which is the atomicity of >>>>> the update on affinity change. If you are moving an interrupt from one >>>>> CPU to the other, it seems you change both the vector number and the >>>>> target address. If that is the case, this isn't atomic, and you may >>>>> end-up with the device generating a message based on a half-applied >>>>> update. >>>> >>>> Are you referring to the callback in 'irq_set_addinity" and >>>> 'irq_compose_msi_msg'? In such case, can you help to recommend a >>>> solution for it (or there's no solution based on such architecture)? It >>>> does not appear such atomy can be enforced from the irq framework level. >>> >>> irq_compose_msi_msg() is only one part of the problem. The core of the >>> issue is that the programming of the end-point is not atomic (you need >>> to update a 32bit payload *and* a 64bit address). >>> >>> A solution to workaround it would be to rework the way you allocate >>> the vectors, making them constant across all CPUs so that only the >>> address changes when changing the affinity. >>> >>> Thanks, >>> >>> M. >>> >>> -- >>> Without deviation from the norm, progress is not possible. >> [2 0001-PCI-iproc-fix-the-base-vector-number-allocation-for-.patch ] >> From df31c9c0333ca4922b7978b30719348e368bea3c Mon Sep 17 00:00:00 2001 >> From: Sandor Bodo-Merle >> Date: Wed, 26 May 2021 17:48:16 +0200 >> Subject: [PATCH] PCI: iproc: fix the base vector number allocation for Multi >> MSI >> MIME-Version: 1.0 >> Content-Type: text/plain; charset=UTF-8 >> Content-Transfer-Encoding: 8bit >> >> Commit fc54bae28818 ("PCI: iproc: Allow allocation of multiple MSIs") >> failed to reserve the proper number of bits from the inner domain. >> Natural alignment of the base vector number was also not guaranteed. >> >> Fixes: fc54bae28818 ("PCI: iproc: Allow allocation of multiple MSIs") >> Reported-by: Pali Rohár >> Signed-off-by: Sandor Bodo-Merle >> --- >> drivers/pci/controller/pcie-iproc-msi.c | 18 ++++++++---------- >> 1 file changed, 8 insertions(+), 10 deletions(-) >> >> diff --git drivers/pci/controller/pcie-iproc-msi.c drivers/pci/controller/pcie-iproc-msi.c >> index eede4e8f3f75..fa2734dd8482 100644 >> --- drivers/pci/controller/pcie-iproc-msi.c >> +++ drivers/pci/controller/pcie-iproc-msi.c >> @@ -252,18 +252,15 @@ static int iproc_msi_irq_domain_alloc(struct irq_domain *domain, >> >> mutex_lock(&msi->bitmap_lock); >> >> - /* Allocate 'nr_cpus' number of MSI vectors each time */ >> - hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0, >> - msi->nr_cpus, 0); >> - if (hwirq < msi->nr_msi_vecs) { >> - bitmap_set(msi->bitmap, hwirq, msi->nr_cpus); >> - } else { >> - mutex_unlock(&msi->bitmap_lock); >> - return -ENOSPC; >> - } >> + /* Allocate 'nr_irqs' multiplied by 'nr_cpus' number of MSI vectors each time */ >> + hwirq = bitmap_find_free_region(msi->bitmap, msi->nr_msi_vecs, >> + order_base_2(msi->nr_cpus * nr_irqs)); >> >> mutex_unlock(&msi->bitmap_lock); >> >> + if (hwirq < 0) >> + return -ENOSPC; >> + >> for (i = 0; i < nr_irqs; i++) { >> irq_domain_set_info(domain, virq + i, hwirq + i, >> &iproc_msi_bottom_irq_chip, >> @@ -284,7 +281,8 @@ static void iproc_msi_irq_domain_free(struct irq_domain *domain, >> mutex_lock(&msi->bitmap_lock); >> >> hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq); >> - bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus); >> + bitmap_release_region(msi->bitmap, hwirq, >> + order_base_2(msi->nr_cpus * nr_irqs)); >> >> mutex_unlock(&msi->bitmap_lock); >> > > This looks reasonable. However, this doesn't change the issue that you > have with SMP systems and Multi-MSI. I'd like to see a more complete > patch (disabling Multi-MSI on SMP, at the very least). > Yeah, agree with you that we want to see this patch at least disables multi-msi when it detects 'num_possible_cpus' > 1. > Thanks, > > M. > --0000000000000b9d7105c3df802b Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQXgYJKoZIhvcNAQcCoIIQTzCCEEsCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg21MIIFDTCCA/WgAwIBAgIQeEqpED+lv77edQixNJMdADANBgkqhkiG9w0BAQsFADBMMSAwHgYD VQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMzETMBEGA1UEChMKR2xvYmFsU2lnbjETMBEGA1UE AxMKR2xvYmFsU2lnbjAeFw0yMDA5MTYwMDAwMDBaFw0yODA5MTYwMDAwMDBaMFsxCzAJBgNVBAYT AkJFMRkwFwYDVQQKExBHbG9iYWxTaWduIG52LXNhMTEwLwYDVQQDEyhHbG9iYWxTaWduIEdDQyBS MyBQZXJzb25hbFNpZ24gMiBDQSAyMDIwMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA vbCmXCcsbZ/a0fRIQMBxp4gJnnyeneFYpEtNydrZZ+GeKSMdHiDgXD1UnRSIudKo+moQ6YlCOu4t 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