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[83.9.32.53]) by smtp.gmail.com with ESMTPSA id v9-20020a2ea449000000b0027fee4c3c29sm2191413ljn.21.2023.01.12.06.32.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 06:32:36 -0800 (PST) Message-ID: <942a6282-5519-8871-5043-229bead87bd8@linaro.org> Date: Thu, 12 Jan 2023 15:32:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 09/13] clk: qcom: cpu-8996: fix PLL configuration sequence Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20230111192004.2509750-1-dmitry.baryshkov@linaro.org> <20230111192004.2509750-10-dmitry.baryshkov@linaro.org> <449be451-f12c-ee14-a5f8-7a1e0d417597@linaro.org> From: Konrad Dybcio In-Reply-To: <449be451-f12c-ee14-a5f8-7a1e0d417597@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 11.01.2023 23:05, Dmitry Baryshkov wrote: > On 11/01/2023 23:08, Konrad Dybcio wrote: >> >> >> On 11.01.2023 20:20, Dmitry Baryshkov wrote: >>> Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux) >>> before PLL configuration. Switch them to the ACD afterwards. >>> >>> Signed-off-by: Dmitry Baryshkov >>> --- >>>   drivers/clk/qcom/clk-cpu-8996.c | 14 ++++++++++++++ >>>   1 file changed, 14 insertions(+) >>> >>> diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c >>> index 571ed52b3026..47c58bb5f21a 100644 >>> --- a/drivers/clk/qcom/clk-cpu-8996.c >>> +++ b/drivers/clk/qcom/clk-cpu-8996.c >>> @@ -432,13 +432,27 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev, >>>   { >>>       int i, ret; >>>   +    /* Select GPLL0 for 300MHz for the both clusters */ >> superfluous 'the' >> >>> +    regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0xc); >>> +    regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0xc); >>> + >>> +    /* Ensure write goes through before PLLs are reconfigured */ >>> +    udelay(5); >> Is this value based on n clock cycles, or 'good enough'? > > Don't know, this is based on downstream direclty. Right, I see it now. > >> >>> + >>>       clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); >>>       clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); >>>       clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); >>>       clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); >>>   +    /* Wait for PLL(s) to lock */ >>> +        udelay(50); >> Weird indentation >> >> Maybe wait_for_pll_enable_lock() to be super sure? > > Does it work for HWFSM PLLs? Not sure, but wait_for_pll_update_ack_clear() should, since it's called by clk_alpha_pll_hwfsm_set_rate() -> __clk_alpha_pll_set_rate() -> clk_alpha_pll_update_latch() -> __clk_alpha_pll_update_latch() Konrad > >> >>> + >>>       qcom_cpu_clk_msm8996_acd_init(regmap); >>>   +    /* Switch clusters to use the ACD leg */ >>> +    regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x2); >>> +    regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x2); >>> + >> No delays here? > > No. Probably it isn't required since there is no additional PLL locking, etc. > >> >> Konrad >>>       for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) { >>>           ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]); >>>           if (ret) >