From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Xu, Quan" <quan.xu@intel.com>
Subject: Re: [PATCH v2 1/2] VT-d: Reduce spin timeout to 1ms,
 which can be boot-time changed.
Date: Fri, 11 Dec 2015 08:45:36 +0000
Message-ID: <945CA011AD5F084CBEA3E851C0AB28894AE593EE@SHSMSX103.ccr.corp.intel.com>
References: <1449739990-66155-1-git-send-email-quan.xu@intel.com>
	<1449739990-66155-2-git-send-email-quan.xu@intel.com>
	<5669CC64.7050407@citrix.com>
	<945CA011AD5F084CBEA3E851C0AB28894AE58FB1@SHSMSX103.ccr.corp.intel.com>
	<566A8B31.2040009@citrix.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
In-Reply-To: <566A8B31.2040009@citrix.com>
Content-Language: en-US
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "Tian, Kevin" <kevin.tian@intel.com>, "Wu, Feng" <feng.wu@intel.com>, "jbeulich@suse.com" <jbeulich@suse.com>, "george.dunlap@eu.citrix.com" <george.dunlap@eu.citrix.com>, "Dong, Eddie" <eddie.dong@intel.com>, "tim@xen.org" <tim@xen.org>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>, "Nakajima,
	Jun" <jun.nakajima@intel.com>, "keir@xen.org" <keir@xen.org>
List-Id: xen-devel@lists.xenproject.org

On 11.12.2015 at 4:37pm, <Andrew Cooper> wrote:
> On 11/12/2015 02:09, Xu, Quan wrote:
> > On 11.12.2015 at 3:03pm, <andrew.cooper3@citrix.com> wrote:
> >> On 10/12/15 09:33, Quan Xu wrote:
> >>> Signed-off-by: Quan Xu <quan.xu@intel.com>


> >> This patch misses a second use of DMAR_OPERATION_TIMEOUT, in
> >> IOMMU_WAIT_OP() which in turn is used in a large number of locations.
> >> All of these locations equally need to be chopped down to a low
> >> number of milliseconds.
> > Andrew, thanks for your comments.
> >
> > I know that DMAR_OPERATION_TIMEOUT should be also chopped down to a
> low number of milliseconds.
> > As Kevin Tian mentioned in 'Revisit VT-d asynchronous flush issue', We
> > also confirmed with hardware team that 1ms is large enough for IOMMU
> internal flush.
> > So I can change DMAR_OPERATION_TIMEOUT from 1000 ms to 1 ms.
> 
> Ok - sounds good.
> 
> >
> > IOMMU_WAIT_OP() is only for VT-d registers read/write, and there is
> > also a panic. We need a further discussion whether or how to remove this
> panic.
> 
> We certainly should see about removing it.
> 

Agreed.

-Quan


> > I can send another patch set to fix it. in this patch set, I want to
> > focus on VT-d QI flush.
> 
> Agreed.
> 
> ~Andrew