Re: [PATCH v9 1/3] dmaengine: ptdma: Initial driver for the AMD PTDMA

[Sanjay R Mehta <sanmehta@amd.com>]

On 6/8/2021 11:09 PM, Vinod Koul wrote:
> [CAUTION: External Email]
> 
> On 02-06-21, 12:22, Sanjay R Mehta wrote:
> 
>> +static int pt_core_execute_cmd(struct ptdma_desc *desc, struct pt_cmd_queue *cmd_q)
>> +{
>> +     bool soc = FIELD_GET(DWORD0_SOC, desc->dw0);
>> +     u8 *q_desc = (u8 *)&cmd_q->qbase[cmd_q->qidx];
>> +     u8 *dp = (u8 *)desc;
> 
> this case seems unnecessary?
> 
>> +int pt_core_perform_passthru(struct pt_cmd_queue *cmd_q,
>> +                          struct pt_passthru_engine *pt_engine)
> 
> Pls align this to preceding open brace, checkpatch with --strict would
> warn you about this
> 
>> +static irqreturn_t pt_core_irq_handler(int irq, void *data)
>> +{
>> +     struct pt_device *pt = data;
>> +     struct pt_cmd_queue *cmd_q = &pt->cmd_q;
>> +     u32 status;
>> +
>> +     pt_core_disable_queue_interrupts(pt);
>> +
>> +     status = ioread32(cmd_q->reg_interrupt_status);
>> +     if (status) {
>> +             cmd_q->int_status = status;
>> +             cmd_q->q_status = ioread32(cmd_q->reg_status);
>> +             cmd_q->q_int_status = ioread32(cmd_q->reg_int_status);
>> +
>> +             /* On error, only save the first error value */
>> +             if ((status & INT_ERROR) && !cmd_q->cmd_error)
>> +                     cmd_q->cmd_error = CMD_Q_ERROR(cmd_q->q_status);
>> +
>> +             /* Acknowledge the interrupt */
>> +             iowrite32(status, cmd_q->reg_interrupt_status);
>> +     }
>> +
>> +     pt_core_enable_queue_interrupts(pt);
>> +
>> +     return IRQ_HANDLED;
> 
> should you always return IRQ_HANDLED, that sounds apt for the if loop
> but not for the non loop case
> 
>> +int pt_core_init(struct pt_device *pt)
>> +{
>> +     char dma_pool_name[MAX_DMAPOOL_NAME_LEN];
>> +     struct pt_cmd_queue *cmd_q = &pt->cmd_q;
>> +     u32 dma_addr_lo, dma_addr_hi;
>> +     struct device *dev = pt->dev;
>> +     struct dma_pool *dma_pool;
>> +     int ret;
>> +
>> +     /* Allocate a dma pool for the queue */
>> +     snprintf(dma_pool_name, sizeof(dma_pool_name), "%s_q", pt->name);
>> +
>> +     dma_pool = dma_pool_create(dma_pool_name, dev,
>> +                                PT_DMAPOOL_MAX_SIZE,
>> +                                PT_DMAPOOL_ALIGN, 0);
>> +     if (!dma_pool) {
>> +             dev_err(dev, "unable to allocate dma pool\n");
> 
> This is superfluous, allocator would warn on failure
> 
>> +static struct pt_device *pt_alloc_struct(struct device *dev)
>> +{
>> +     struct pt_device *pt;
>> +
>> +     pt = devm_kzalloc(dev, sizeof(*pt), GFP_KERNEL);
>> +
>> +     if (!pt)
>> +             return NULL;
>> +     pt->dev = dev;
>> +     pt->ord = atomic_inc_return(&pt_ordinal);
> 
> What is the use of this number?
> 

There are eight similar instances of this DMA engine on AMD SOC.
It is to differentiate each of these instances.

- Sanjay