From mboxrd@z Thu Jan  1 00:00:00 1970
From: Bhadram Varka <vbhadram@nvidia.com>
Subject: Re: STMMAC driver with TSO enabled issue
Date: Mon, 28 May 2018 14:45:45 +0530
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References: <fcb38ad0-a6e4-ce65-ead0-eb98ff0913a5@nvidia.com>
 <be22393f-bdea-0171-ea2d-04f8e9b9555f@synopsys.com>
 <89c0a735-9e34-89c6-7692-579e48dadaa6@nvidia.com>
 <77c98a42-195f-b597-711d-8c2e8b55f266@synopsys.com>
 <f423213d-4092-f77a-3bc5-4f4198bb222c@synopsys.com>
 <5309d046-fc6f-bc63-06dc-6cc98276dce4@nvidia.com>
 <77ff3baf-fec5-f0a2-9fdf-caa63d4944d0@synopsys.com>
 <b624e09b-2e66-97ae-5ba8-8a00caa3e679@nvidia.com>
 <a7c17a56-dc40-2bd2-b621-cf73db50cd6e@synopsys.com>
 <c1c9025e-f75b-9ae1-4513-24615308e0af@nvidia.com>
 <06ec3e2e-c41a-5f19-ffd8-51c5453d586b@synopsys.com>
 <3143ce1f-30e7-6b8d-06b5-6048abab54bc@nvidia.com>
 <78914761-0375-5929-ed88-5225e0e260b9@synopsys.com>
 <94cda7c4-127c-cae1-e51e-8853224065e2@nvidia.com>
 <a806ab0c-40b8-2d64-4f7b-4e98a3d03c1b@synopsys.com>
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To: Jose Abreu <Jose.Abreu@synopsys.com>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        Joao Pinto <Joao.Pinto@synopsys.com>
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Hi Jose,

On 5/25/2018 8:02 PM, Jose Abreu wrote:
> On 25-05-2018 15:25, Bhadram Varka wrote:
>> Hi Jose,
>>
>> On 5/25/2018 7:35 PM, Jose Abreu wrote:
>>> Hi Bhadram,
>>>
>>> On 25-05-2018 05:41, Bhadram Varka wrote:
>>>> Hi Jose,
>>>>
>>>> On 5/24/2018 3:01 PM, Jose Abreu wrote:
>>>>> Hi Bhadram,
>>>>>
>>>>> On 24-05-2018 06:58, Bhadram Varka wrote:
>>>>>>
>>>>>> After some time if check Tx descriptor status - then I see
>>>>>> only
>>>>>> below
>>>>>>
>>>>>> [..]
>>>>>> [85788.286730] 027 [0x827951b0]: 0xf854f000 0x0 0x16d8
>>>>>> 0x90000000
>>>>>>
>>>>>> index 025 and 026 descriptors processed but not index 027.
>>>>>>
>>>>>> At this stage Tx DMA is always in below state -
>>>>>>
>>>>>> ■ 3'b011: Running (Reading Data from system memory
>>>>>> buffer and queuing it to the Tx buffer (Tx FIFO))
>>>>>
>>>>> Thats strange, I think the descriptors look okay though. I will
>>>>> need the registers values (before the lock) and, if
>>>>> possible, the
>>>>> git bisect output.
>>>>
>>>> Attaching the register dump file after the issue observed.
>>>> Please check once.
>>>>
>>>
>>> ----->8-----
>>> 0x112c = 0x0000003F
>>> 0x11ac = 0x0000003F
>>> 0x122c = 0x0000003F
>>> 0x12ac = 0x0000003F
>>>
>>> 0x1130 = 0x0000003F
>>> 0x11b0 = 0x0000003F
>>> 0x1230 = 0x0000003F
>>> 0x12b0 = 0x0000003F
>>> ----->8-----
>>>
>>> This can't be right, it should be DMA_{RX/TX}_SIZE - 1 = 511. Did
>>> you change these values in the code?
>>>
>>
>> Yes. I have changed the descriptor length to 64 - so that
>> searching for the current descriptor status would be easy.
> 
> Ok, it shouldn't impact anything. The only thing I'm remembering
> now is that you can have TSO not enabled in all DMA channels (HW
> configuration allows this). Please check if TSO in single-queue
> works.
TSO works fine if only single queue enabled. I don't see any limitation 
from HW side because TSO works fine with other driver which we received 
from Synopsys with IP drop.

Thanks,
Bhadram.