[PATCH 00/15] ppc/ppc405: decade cleanup

[PATCH 00/15] ppc/ppc405: decade cleanup

[Cédric Le Goater]

Hello,

The goal of these changes is to refresh the QEMU ref405ep machine and
enable boot from a Linux kernel without relying on a U-Boot firmware.
The reason for doing so is that we are unable to find a "ppc405_rom.bin"
firmware image or a flash image for the 405EP machines.

Thomas fought is way through on a v2015.10 U-Boot and taihu defconfig
and provided a compatible image available here :

 https://gitlab.com/huth/u-boot/-/tree/taihu/

With this image, QEMU reaches the U-Boot prompt (with a simple
workaround in the SDRAM).

On the Linux side, the only available 405EP CPU board is the one for
the ESTeem 195E (PPC405EP) SBC (hotfoot). It was added in 2009. The
board information structure in Linux, in U-Boot and in QEMU are not in
sync and the hotfoot board also adds its own flavor because the FW was
an ancient U-Boot without dual ethernet support [1].

For this kernel to be loaded by the U-Boot image provided by Thomas,
we either need to modify U-Boot or Linux. The same question arise for
QEMU, see the last patch of this series which is controversial. Please
advise !

Thanks,

C.

[1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html

Cédric Le Goater (14):
  ppc/ppc405: Change kernel load address
  ppc: Add trace-events for DCR accesses
  ppc/ppc405: Convert printfs to trace-events
  ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo()
  ppc/ppc405: Change ppc405ep_init() return value
  ppc/ppc405: Add some address space definitions
  ppc/ppc405: Remove flash support
  ppc/ppc405: Rework FW load
  ppc/ppc405: Introduce ppc405_set_default_bootinfo()
  ppc/ppc405: Fix boot from kernel
  ppc/ppc405: Change default PLL values at reset
  ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information
  ppc/ppc405: Add update of bi_procfreq field
  ppc/ppc405: Update U-Boot board information for hotfoot

Thomas Huth (1):
  ppc: Mark the 'taihu' machine as deprecated

 docs/about/deprecated.rst |   9 ++
 hw/ppc/ppc405.h           |  14 +-
 hw/ppc/ppc.c              |   2 +
 hw/ppc/ppc405_boards.c    | 245 ++++++++++++++++++----------------
 hw/ppc/ppc405_uc.c        | 270 +++++++++++++++++++++-----------------
 hw/ppc/trace-events       |  23 ++++
 6 files changed, 327 insertions(+), 236 deletions(-)

-- 
2.31.1

[PATCH 01/15] ppc/ppc405: Change kernel load address

[Cédric Le Goater]

The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :

	"kernel_addr_r=1000000\0"
	"fdt_addr_r=1800000\0"
	"ramdisk_addr_r=1900000\0"

The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both boards have a very similar
address space layout.

Also, if loaded at address 0, U-Boot will partially overwrite the
uImage because of a bug in get_ram_size() (U-Boot v2015.10) not
restoring properly the probed RAM contents and because the exception
vectors are installed in the same range. Finally, a gzipped kernel
image will be uncompressed at 0x0. These are all good reasons for not
mappping a kernel image at this address.

Change the kernel load address to match U-Boot expectations and fix
loading.

Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211202191446.1292125-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405_boards.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 972a7a4a3e5d..b4249f4626e6 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -45,7 +45,7 @@
 #define BIOS_FILENAME "ppc405_rom.bin"
 #define BIOS_SIZE (2 * MiB)
 
-#define KERNEL_LOAD_ADDR 0x00000000
+#define KERNEL_LOAD_ADDR 0x01000000
 #define INITRD_LOAD_ADDR 0x01800000
 
 #define USE_FLASH_BIOS
-- 
2.31.1

[PATCH 02/15] ppc: Mark the 'taihu' machine as deprecated

[Cédric Le Goater]

From: Thomas Huth <thuth@redhat.com>

The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
except for some external periphery. However, the periphery of the 'taihu'
machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
been implemented), so there is not much value added by this board. The users
can use the 'ref405ep' machine to test their PPC405 code instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211203164904.290954-2-thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 docs/about/deprecated.rst | 9 +++++++++
 hw/ppc/ppc405_boards.c    | 1 +
 2 files changed, 10 insertions(+)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index ff7488cb63b9..5693abb663e3 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -315,6 +315,15 @@ This machine is deprecated because we have enough AST2500 based OpenPOWER
 machines. It can be easily replaced by the ``witherspoon-bmc`` or the
 ``romulus-bmc`` machines.
 
+PPC 405 ``taihu`` machine (since 7.0)
+'''''''''''''''''''''''''''''''''''''
+
+The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
+except for some external periphery. However, the periphery of the ``taihu``
+machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
+been implemented), so there is not much value added by this board. Use the
+``ref405ep`` machine instead.
+
 Backend options
 ---------------
 
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index b4249f4626e6..f1623aa622a6 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -547,6 +547,7 @@ static void taihu_class_init(ObjectClass *oc, void *data)
     mc->init = taihu_405ep_init;
     mc->default_ram_size = 0x08000000;
     mc->default_ram_id = "taihu_405ep.ram";
+    mc->deprecation_reason = "incomplete, use 'ref405ep' instead";
 }
 
 static const TypeInfo taihu_type = {
-- 
2.31.1

[PATCH 03/15] ppc: Add trace-events for DCR accesses

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc.c        | 2 ++
 hw/ppc/trace-events | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index e8127599c907..818d75798584 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1367,6 +1367,7 @@ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
     if (dcr->dcr_read == NULL)
         goto error;
     *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
+    trace_ppc_dcr_read(dcrn, *valp);
 
     return 0;
 
@@ -1386,6 +1387,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
     dcr = &dcr_env->dcrn[dcrn];
     if (dcr->dcr_write == NULL)
         goto error;
+    trace_ppc_dcr_write(dcrn, val);
     (*dcr->dcr_write)(dcr->opaque, dcrn, val);
 
     return 0;
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 3bf43fa340fe..602adb83157b 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -119,6 +119,9 @@ ppc_irq_set_state(const char *name, uint32_t level) "\"%s\" level %d"
 ppc_irq_reset(const char *name) "%s"
 ppc_irq_cpu(const char *action) "%s"
 
+ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x"
+ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x"
+
 # prep_systemio.c
 prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
 prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
-- 
2.31.1

[PATCH 04/15] ppc/ppc405: Convert printfs to trace-events

[Cédric Le Goater]

and one error message to a LOG_GUEST_ERROR.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405_uc.c  | 159 +++++++++++++++-----------------------------
 hw/ppc/trace-events |  20 ++++++
 2 files changed, 74 insertions(+), 105 deletions(-)

diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e632c408bdf8..e14d61e9b899 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -25,6 +25,7 @@
 #include "qemu/osdep.h"
 #include "qemu/units.h"
 #include "qapi/error.h"
+#include "qemu/log.h"
 #include "cpu.h"
 #include "hw/ppc/ppc.h"
 #include "hw/i2c/ppc4xx_i2c.h"
@@ -38,15 +39,7 @@
 #include "hw/intc/ppc-uic.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
-
-//#define DEBUG_OPBA
-//#define DEBUG_SDRAM
-//#define DEBUG_GPIO
-//#define DEBUG_SERIAL
-//#define DEBUG_OCM
-//#define DEBUG_GPT
-//#define DEBUG_CLOCKS
-//#define DEBUG_CLOCKS_LL
+#include "trace.h"
 
 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
                                 uint32_t flags)
@@ -287,13 +280,9 @@ struct ppc4xx_opba_t {
 
 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
 {
-    ppc4xx_opba_t *opba;
+    ppc4xx_opba_t *opba = opaque;
     uint32_t ret;
 
-#ifdef DEBUG_OPBA
-    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
-    opba = opaque;
     switch (addr) {
     case 0x00:
         ret = opba->cr;
@@ -306,19 +295,17 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
         break;
     }
 
+    trace_opba_readb(addr, ret);
     return ret;
 }
 
 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
                         unsigned size)
 {
-    ppc4xx_opba_t *opba;
+    ppc4xx_opba_t *opba = opaque;
+
+    trace_opba_writeb(addr, value);
 
-#ifdef DEBUG_OPBA
-    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
-           value);
-#endif
-    opba = opaque;
     switch (addr) {
     case 0x00:
         opba->cr = value & 0xF8;
@@ -353,10 +340,9 @@ static void ppc4xx_opba_init(hwaddr base)
 {
     ppc4xx_opba_t *opba;
 
+    trace_opba_init(base);
+
     opba = g_malloc0(sizeof(ppc4xx_opba_t));
-#ifdef DEBUG_OPBA
-    printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
-#endif
     memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
     memory_region_add_subregion(get_system_memory(), base, &opba->io);
     qemu_register_reset(ppc4xx_opba_reset, opba);
@@ -707,20 +693,14 @@ struct ppc405_gpio_t {
 
 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size)
 {
-#ifdef DEBUG_GPIO
-    printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size);
-#endif
-
+    trace_ppc405_gpio_read(addr, size);
     return 0;
 }
 
 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value,
                               unsigned size)
 {
-#ifdef DEBUG_GPIO
-    printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n",
-           __func__, addr, size, value);
-#endif
+    trace_ppc405_gpio_write(addr, size, value);
 }
 
 static const MemoryRegionOps ppc405_gpio_ops = {
@@ -737,10 +717,9 @@ static void ppc405_gpio_init(hwaddr base)
 {
     ppc405_gpio_t *gpio;
 
+    trace_ppc405_gpio_init(base);
+
     gpio = g_malloc0(sizeof(ppc405_gpio_t));
-#ifdef DEBUG_GPIO
-    printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
-#endif
     memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
     memory_region_add_subregion(get_system_memory(), base, &gpio->io);
     qemu_register_reset(&ppc405_gpio_reset, gpio);
@@ -770,25 +749,19 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
                                  uint32_t isarc, uint32_t isacntl,
                                  uint32_t dsarc, uint32_t dsacntl)
 {
-#ifdef DEBUG_OCM
-    printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
-           " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
-           " (%08" PRIx32 " %08" PRIx32 ")\n",
-           isarc, isacntl, dsarc, dsacntl,
-           ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
-#endif
+    trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc,
+                              ocm->isacntl, ocm->dsarc, ocm->dsacntl);
+
     if (ocm->isarc != isarc ||
         (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
         if (ocm->isacntl & 0x80000000) {
             /* Unmap previously assigned memory region */
-            printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
+            trace_ocm_unmap("ISA", ocm->isarc);
             memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
         }
         if (isacntl & 0x80000000) {
             /* Map new instruction memory region */
-#ifdef DEBUG_OCM
-            printf("OCM map ISA %08" PRIx32 "\n", isarc);
-#endif
+            trace_ocm_map("ISA", isarc);
             memory_region_add_subregion(get_system_memory(), isarc,
                                         &ocm->isarc_ram);
         }
@@ -799,9 +772,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
             /* Beware not to unmap the region we just mapped */
             if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
                 /* Unmap previously assigned memory region */
-#ifdef DEBUG_OCM
-                printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
-#endif
+                trace_ocm_unmap("DSA", ocm->dsarc);
                 memory_region_del_subregion(get_system_memory(),
                                             &ocm->dsarc_ram);
             }
@@ -810,9 +781,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
             /* Beware not to remap the region we just mapped */
             if (!(isacntl & 0x80000000) || dsarc != isarc) {
                 /* Map new data memory region */
-#ifdef DEBUG_OCM
-                printf("OCM map DSA %08" PRIx32 "\n", dsarc);
-#endif
+                trace_ocm_map("DSA", dsarc);
                 memory_region_add_subregion(get_system_memory(), dsarc,
                                             &ocm->dsarc_ram);
             }
@@ -988,14 +957,12 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
 
 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
 {
-    ppc4xx_gpt_t *gpt;
+    ppc4xx_gpt_t *gpt = opaque;
     uint32_t ret;
     int idx;
 
-#ifdef DEBUG_GPT
-    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-#endif
-    gpt = opaque;
+    trace_ppc4xx_gpt_read(addr, size);
+
     switch (addr) {
     case 0x00:
         /* Time base counter */
@@ -1044,14 +1011,11 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size)
 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value,
                              unsigned size)
 {
-    ppc4xx_gpt_t *gpt;
+    ppc4xx_gpt_t *gpt = opaque;
     int idx;
 
-#ifdef DEBUG_I2C
-    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
-           value);
-#endif
-    gpt = opaque;
+    trace_ppc4xx_gpt_write(addr, size, value);
+
     switch (addr) {
     case 0x00:
         /* Time base counter */
@@ -1144,14 +1108,13 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
     ppc4xx_gpt_t *gpt;
     int i;
 
+    trace_ppc4xx_gpt_init(base);
+
     gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
     for (i = 0; i < 5; i++) {
         gpt->irqs[i] = irqs[i];
     }
     gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
-#ifdef DEBUG_GPT
-    printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
-#endif
     memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
     memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
     qemu_register_reset(ppc4xx_gpt_reset, gpt);
@@ -1215,17 +1178,14 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
     VCO_out = 0;
     if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
         M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
-#ifdef DEBUG_CLOCKS_LL
-        printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
-#endif
+        trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M);
         D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
-#ifdef DEBUG_CLOCKS_LL
-        printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
-#endif
+        trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D);
         VCO_out = (uint64_t)cpc->sysclk * M * D;
         if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
             /* Error - unlock the PLL */
-            printf("VCO out of range %" PRIu64 "\n", VCO_out);
+            qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n",
+                          VCO_out);
 #if 0
             cpc->pllmr[1] &= ~0x80000000;
             goto pll_bypass;
@@ -1246,54 +1206,43 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
     }
     /* Now, compute all other clocks */
     D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
-#ifdef DEBUG_CLOCKS_LL
-    printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
-#endif
+     trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D);
     CPU_clk = PLL_out / D;
     D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
-#ifdef DEBUG_CLOCKS_LL
-    printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
-#endif
+    trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D);
     PLB_clk = CPU_clk / D;
     D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
-#ifdef DEBUG_CLOCKS_LL
-    printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
-#endif
+    trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D);
     OPB_clk = PLB_clk / D;
     D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
-#ifdef DEBUG_CLOCKS_LL
-    printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
-#endif
+    trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D);
     EBC_clk = PLB_clk / D;
     D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
-#ifdef DEBUG_CLOCKS_LL
-    printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
-#endif
+    trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D);
     MAL_clk = PLB_clk / D;
     D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
-#ifdef DEBUG_CLOCKS_LL
-    printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
-#endif
+    trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D);
     PCI_clk = PLB_clk / D;
     D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
-#ifdef DEBUG_CLOCKS_LL
-    printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
-#endif
+    trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D);
     UART0_clk = PLL_out / D;
     D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
-#ifdef DEBUG_CLOCKS_LL
-    printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
-#endif
+    trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D);
     UART1_clk = PLL_out / D;
-#ifdef DEBUG_CLOCKS
-    printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
-           " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
-    printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
-           " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
-           " UART1 %" PRIu32 "\n",
-           CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
-           UART0_clk, UART1_clk);
-#endif
+
+    if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) {
+        g_autofree char *trace = g_strdup_printf(
+            "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
+            " PLL out %" PRIu64 " Hz\n"
+            "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
+            " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
+            " UART1 %" PRIu32 "\n",
+            cpc->sysclk, VCO_out, PLL_out,
+            CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
+            UART0_clk, UART1_clk);
+        trace_ppc405ep_clocks_setup(trace);
+    }
+
     /* Setup CPU clocks */
     clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
     /* Setup PLB clock */
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 602adb83157b..ada644652d94 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -144,3 +144,23 @@ ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of
 ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64
 ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
 ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32
+
+# ppc405_boards.c
+opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
+opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64
+opba_init(uint64_t addr) "offet 0x%" PRIx64
+
+ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
+ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
+ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64
+
+ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRIx32 " 0x%08" PRIx32 ")"
+ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32
+ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32
+
+ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
+ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
+ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64
+
+ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) "%s 0x%1" PRIx32 " %d"
+ppc405ep_clocks_setup(const char *trace) "%s"
-- 
2.31.1

[PATCH 05/15] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo()

[Cédric Le Goater]

It was introduced in commit b8d3f5d12642 ("Add flags to support
PowerPC 405 bootinfos variations.") but since its value has always
been set to '1'.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405.h        | 3 +--
 hw/ppc/ppc405_boards.c | 2 +-
 hw/ppc/ppc405_uc.c     | 8 +++-----
 3 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index c58f739886a6..4cb77aca5690 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -56,8 +56,7 @@ struct ppc4xx_bd_info_t {
 };
 
 /* PowerPC 405 core */
-ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
-                                uint32_t flags);
+ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd);
 
 void ppc4xx_plb_init(CPUPPCState *env);
 void ppc405_ebc_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index f1623aa622a6..2ac38c86a643 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -261,7 +261,7 @@ static void ref405ep_init(MachineState *machine)
         bd.bi_plb_busfreq = 33333333;
         bd.bi_pci_busfreq = 33333333;
         bd.bi_opbfreq = 33333333;
-        bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
+        bdloc = ppc405_set_bootinfo(env, &bd);
         env->gpr[3] = bdloc;
         kernel_base = KERNEL_LOAD_ADDR;
         /* now we can load the kernel */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e14d61e9b899..6806d6be31d5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -41,8 +41,7 @@
 #include "qapi/error.h"
 #include "trace.h"
 
-ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
-                                uint32_t flags)
+ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
 {
     CPUState *cs = env_cpu(env);
     ram_addr_t bdloc;
@@ -81,9 +80,8 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
         stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
     }
     n = 0x6A;
-    if (flags & 0x00000001) {
-        for (i = 0; i < 6; i++)
-            stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
+    for (i = 0; i < 6; i++) {
+        stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
     }
     stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
     n += 4;
-- 
2.31.1

[PATCH 06/15] ppc/ppc405: Change ppc405ep_init() return value

[Cédric Le Goater]

I will be useful to rework the boot from Linux.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405.h        | 2 +-
 hw/ppc/ppc405_boards.c | 6 +++++-
 hw/ppc/ppc405_uc.c     | 4 ++--
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 4cb77aca5690..ad5f4026b5db 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -61,7 +61,7 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd);
 void ppc4xx_plb_init(CPUPPCState *env);
 void ppc405_ebc_init(CPUPPCState *env);
 
-CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
+PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
                         MemoryRegion ram_memories[2],
                         hwaddr ram_bases[2],
                         hwaddr ram_sizes[2],
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 2ac38c86a643..fcdb6d4cf8a0 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -145,6 +145,7 @@ static void ref405ep_init(MachineState *machine)
     const char *initrd_filename = machine->initrd_filename;
     char *filename;
     ppc4xx_bd_info_t bd;
+    PowerPCCPU *cpu;
     CPUPPCState *env;
     DeviceState *dev;
     SysBusDevice *s;
@@ -180,8 +181,11 @@ static void ref405ep_init(MachineState *machine)
     memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
     ram_bases[1] = 0x00000000;
     ram_sizes[1] = 0x00000000;
-    env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
+
+    cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
                         33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
+    env = &cpu->env;
+
     /* allocate SRAM */
     sram_size = 512 * KiB;
     memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 6806d6be31d5..4ad81695e80a 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1391,7 +1391,7 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
 #endif
 }
 
-CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
+PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem,
                         MemoryRegion ram_memories[2],
                         hwaddr ram_bases[2],
                         hwaddr ram_sizes[2],
@@ -1490,5 +1490,5 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
     /* CPU control */
     ppc405ep_cpc_init(env, clk_setup, sysclk);
 
-    return env;
+    return cpu;
 }
-- 
2.31.1

[PATCH 07/15] ppc/ppc405: Add some address space definitions

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405.h        |  7 +++++++
 hw/ppc/ppc405_boards.c | 16 +++++++---------
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ad5f4026b5db..ea48c3626908 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -27,6 +27,13 @@
 
 #include "hw/ppc/ppc4xx.h"
 
+#define PPC405EP_SDRAM_BASE 0x00000000
+#define PPC405EP_NVRAM_BASE 0xF0000000
+#define PPC405EP_FPGA_BASE  0xF0300000
+#define PPC405EP_SRAM_BASE  0xFFF00000
+#define PPC405EP_SRAM_SIZE  (512 * KiB)
+#define PPC405EP_FLASH_BASE 0xFFF80000
+
 /* Bootinfo as set-up by u-boot */
 typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
 struct ppc4xx_bd_info_t {
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index fcdb6d4cf8a0..60dc81fa4880 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -154,7 +154,6 @@ static void ref405ep_init(MachineState *machine)
     ram_addr_t bdloc;
     MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
     hwaddr ram_bases[2], ram_sizes[2];
-    target_ulong sram_size;
     long bios_size;
     //int phy_addr = 0;
     //static int phy_addr = 1;
@@ -187,10 +186,9 @@ static void ref405ep_init(MachineState *machine)
     env = &cpu->env;
 
     /* allocate SRAM */
-    sram_size = 512 * KiB;
-    memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
+    memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
                            &error_fatal);
-    memory_region_add_subregion(sysmem, 0xFFF00000, sram);
+    memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
     /* allocate and load BIOS */
 #ifdef USE_FLASH_BIOS
     dinfo = drive_get(IF_PFLASH, 0, 0);
@@ -230,24 +228,24 @@ static void ref405ep_init(MachineState *machine)
         }
     }
     /* Register FPGA */
-    ref405ep_fpga_init(sysmem, 0xF0300000);
+    ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
     /* Register NVRAM */
     dev = qdev_new("sysbus-m48t08");
     qdev_prop_set_int32(dev, "base-year", 1968);
     s = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(s, &error_fatal);
-    sysbus_mmio_map(s, 0, 0xF0000000);
+    sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
     /* Load kernel */
     linux_boot = (kernel_filename != NULL);
     if (linux_boot) {
         memset(&bd, 0, sizeof(bd));
-        bd.bi_memstart = 0x00000000;
+        bd.bi_memstart = PPC405EP_SDRAM_BASE;
         bd.bi_memsize = machine->ram_size;
         bd.bi_flashstart = -bios_size;
         bd.bi_flashsize = -bios_size;
         bd.bi_flashoffset = 0;
-        bd.bi_sramstart = 0xFFF00000;
-        bd.bi_sramsize = sram_size;
+        bd.bi_sramstart = PPC405EP_SRAM_BASE;
+        bd.bi_sramsize = PPC405EP_SRAM_SIZE;
         bd.bi_bootflags = 0;
         bd.bi_intfreq = 133333333;
         bd.bi_busfreq = 33333333;
-- 
2.31.1

[PATCH 08/15] ppc/ppc405: Remove flash support

[Cédric Le Goater]

It is currently impossible to find a "ppc405_rom.bin" firmware file or
a full flash image for the PPC405EP evalution board. Even if it should
be technically possible to recreate such an image, it's unlikely that
anyone will do it since the board is obsolete and support in QEMU has
been broken for about 10 years.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405_boards.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 60dc81fa4880..a385e8f15070 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -161,7 +161,6 @@ static void ref405ep_init(MachineState *machine)
     long kernel_size, initrd_size;
     int linux_boot;
     int len;
-    DriveInfo *dinfo;
     MemoryRegion *sysmem = get_system_memory();
     DeviceState *uicdev;
 
@@ -189,19 +188,8 @@ static void ref405ep_init(MachineState *machine)
     memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
                            &error_fatal);
     memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
+
     /* allocate and load BIOS */
-#ifdef USE_FLASH_BIOS
-    dinfo = drive_get(IF_PFLASH, 0, 0);
-    if (dinfo) {
-        bios_size = 8 * MiB;
-        pflash_cfi02_register((uint32_t)(-bios_size),
-                              "ef405ep.bios", bios_size,
-                              blk_by_legacy_dinfo(dinfo),
-                              64 * KiB, 1,
-                              2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
-                              1);
-    } else
-#endif
     {
         bios = g_new(MemoryRegion, 1);
         memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
-- 
2.31.1

[PATCH 09/15] ppc/ppc405: Rework FW load

[Cédric Le Goater]

QEMU installs a custom U-Boot in-memory descriptor to share board
information with Linux, which means that the QEMU machine was
initially designed to support booting Linux directly without using the
loaded FW. But, it's not that simple because the CPU still starts at
address 0xfffffffc where nothing is currently mapped. Support must
have been broken these last years.

Since we can not find a "ppc405_rom.bin" firmware file, request one to
be specified on the command line. A consequence of this change is that
the machine can be booted directly from Linux without any FW being
loaded. This is still broken and the CPU start address will be fixed
in the next changes.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405_boards.c | 45 +++++++++++++++++++-----------------------
 1 file changed, 20 insertions(+), 25 deletions(-)

diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index a385e8f15070..cfed43dba2f3 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -139,24 +139,19 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
 static void ref405ep_init(MachineState *machine)
 {
     MachineClass *mc = MACHINE_GET_CLASS(machine);
-    const char *bios_name = machine->firmware ?: BIOS_FILENAME;
     const char *kernel_filename = machine->kernel_filename;
     const char *kernel_cmdline = machine->kernel_cmdline;
     const char *initrd_filename = machine->initrd_filename;
-    char *filename;
     ppc4xx_bd_info_t bd;
     PowerPCCPU *cpu;
     CPUPPCState *env;
     DeviceState *dev;
     SysBusDevice *s;
-    MemoryRegion *bios;
     MemoryRegion *sram = g_new(MemoryRegion, 1);
     ram_addr_t bdloc;
     MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
     hwaddr ram_bases[2], ram_sizes[2];
-    long bios_size;
-    //int phy_addr = 0;
-    //static int phy_addr = 1;
+    long bios_size = -1;
     target_ulong kernel_base, initrd_base;
     long kernel_size, initrd_size;
     int linux_boot;
@@ -190,31 +185,31 @@ static void ref405ep_init(MachineState *machine)
     memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
 
     /* allocate and load BIOS */
-    {
-        bios = g_new(MemoryRegion, 1);
+    if (machine->firmware) {
+        MemoryRegion *bios = g_new(MemoryRegion, 1);
+        g_autofree char *filename;
+
         memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
                                &error_fatal);
 
-        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
-        if (filename) {
-            bios_size = load_image_size(filename,
-                                        memory_region_get_ram_ptr(bios),
-                                        BIOS_SIZE);
-            g_free(filename);
-            if (bios_size < 0) {
-                error_report("Could not load PowerPC BIOS '%s'", bios_name);
-                exit(1);
-            }
-            bios_size = (bios_size + 0xfff) & ~0xfff;
-            memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
-        } else if (!qtest_enabled() || kernel_filename != NULL) {
-            error_report("Could not load PowerPC BIOS '%s'", bios_name);
+        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
+        if (!filename) {
+            error_report("Could not find firmware '%s'", machine->firmware);
+            exit(1);
+        }
+
+        bios_size = load_image_size(filename,
+                                    memory_region_get_ram_ptr(bios),
+                                    BIOS_SIZE);
+        if (bios_size < 0) {
+            error_report("Could not load PowerPC BIOS '%s'", machine->firmware);
             exit(1);
-        } else {
-            /* Avoid an uninitialized variable warning */
-            bios_size = -1;
         }
+
+        bios_size = (bios_size + 0xfff) & ~0xfff;
+        memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
     }
+
     /* Register FPGA */
     ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
     /* Register NVRAM */
-- 
2.31.1

[PATCH 10/15] ppc/ppc405: Introduce ppc405_set_default_bootinfo()

[Cédric Le Goater]

This routine is a small helper to cleanup the code. The update of the
flash fields were removed because there are not of any use when booting
from a Linux kernel image. It should be functionally equivalent.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405.h        |  2 +-
 hw/ppc/ppc405_boards.c | 28 +---------------------------
 hw/ppc/ppc405_uc.c     | 41 ++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 42 insertions(+), 29 deletions(-)

diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ea48c3626908..6fb8b41bbc77 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -63,7 +63,7 @@ struct ppc4xx_bd_info_t {
 };
 
 /* PowerPC 405 core */
-ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd);
+ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
 
 void ppc4xx_plb_init(CPUPPCState *env);
 void ppc405_ebc_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index cfed43dba2f3..71a652e2d846 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -142,7 +142,6 @@ static void ref405ep_init(MachineState *machine)
     const char *kernel_filename = machine->kernel_filename;
     const char *kernel_cmdline = machine->kernel_cmdline;
     const char *initrd_filename = machine->initrd_filename;
-    ppc4xx_bd_info_t bd;
     PowerPCCPU *cpu;
     CPUPPCState *env;
     DeviceState *dev;
@@ -221,32 +220,7 @@ static void ref405ep_init(MachineState *machine)
     /* Load kernel */
     linux_boot = (kernel_filename != NULL);
     if (linux_boot) {
-        memset(&bd, 0, sizeof(bd));
-        bd.bi_memstart = PPC405EP_SDRAM_BASE;
-        bd.bi_memsize = machine->ram_size;
-        bd.bi_flashstart = -bios_size;
-        bd.bi_flashsize = -bios_size;
-        bd.bi_flashoffset = 0;
-        bd.bi_sramstart = PPC405EP_SRAM_BASE;
-        bd.bi_sramsize = PPC405EP_SRAM_SIZE;
-        bd.bi_bootflags = 0;
-        bd.bi_intfreq = 133333333;
-        bd.bi_busfreq = 33333333;
-        bd.bi_baudrate = 115200;
-        bd.bi_s_version[0] = 'Q';
-        bd.bi_s_version[1] = 'M';
-        bd.bi_s_version[2] = 'U';
-        bd.bi_s_version[3] = '\0';
-        bd.bi_r_version[0] = 'Q';
-        bd.bi_r_version[1] = 'E';
-        bd.bi_r_version[2] = 'M';
-        bd.bi_r_version[3] = 'U';
-        bd.bi_r_version[4] = '\0';
-        bd.bi_procfreq = 133333333;
-        bd.bi_plb_busfreq = 33333333;
-        bd.bi_pci_busfreq = 33333333;
-        bd.bi_opbfreq = 33333333;
-        bdloc = ppc405_set_bootinfo(env, &bd);
+        bdloc = ppc405_set_bootinfo(env, machine->ram_size);
         env->gpr[3] = bdloc;
         kernel_base = KERNEL_LOAD_ADDR;
         /* now we can load the kernel */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 4ad81695e80a..303af584443d 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -41,7 +41,35 @@
 #include "qapi/error.h"
 #include "trace.h"
 
-ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
+static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
+                                        ram_addr_t ram_size)
+{
+        memset(bd, 0, sizeof(*bd));
+
+        bd->bi_memstart = PPC405EP_SDRAM_BASE;
+        bd->bi_memsize = ram_size;
+        bd->bi_sramstart = PPC405EP_SRAM_BASE;
+        bd->bi_sramsize = PPC405EP_SRAM_SIZE;
+        bd->bi_bootflags = 0;
+        bd->bi_intfreq = 133333333;
+        bd->bi_busfreq = 33333333;
+        bd->bi_baudrate = 115200;
+        bd->bi_s_version[0] = 'Q';
+        bd->bi_s_version[1] = 'M';
+        bd->bi_s_version[2] = 'U';
+        bd->bi_s_version[3] = '\0';
+        bd->bi_r_version[0] = 'Q';
+        bd->bi_r_version[1] = 'E';
+        bd->bi_r_version[2] = 'M';
+        bd->bi_r_version[3] = 'U';
+        bd->bi_r_version[4] = '\0';
+        bd->bi_procfreq = 133333333;
+        bd->bi_plb_busfreq = 33333333;
+        bd->bi_pci_busfreq = 33333333;
+        bd->bi_opbfreq = 33333333;
+}
+
+static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
 {
     CPUState *cs = env_cpu(env);
     ram_addr_t bdloc;
@@ -93,6 +121,17 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
     return bdloc;
 }
 
+ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
+{
+    ppc4xx_bd_info_t bd;
+
+    memset(&bd, 0, sizeof(bd));
+
+    ppc405_set_default_bootinfo(&bd, ram_size);
+
+    return __ppc405_set_bootinfo(env, &bd);
+}
+
 /*****************************************************************************/
 /* Shared peripherals */
 
-- 
2.31.1

[PATCH 11/15] ppc/ppc405: Fix boot from kernel

[Cédric Le Goater]

The machine can already boot with kernel and initrd U-boot images if a
firmware is loaded first. Adapt and improve the load sequence to let
the machine boot directly from a Linux kernel ELF image and a usual
initrd image if a firmware image is not provided. For that, install a
custom CPU reset handler to setup the registers and to start the CPU
from the Linux kernel entry point.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405_boards.c | 145 +++++++++++++++++++++++++++++------------
 1 file changed, 102 insertions(+), 43 deletions(-)

diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 71a652e2d846..3ae2b36373a5 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -41,6 +41,7 @@
 #include "qemu/error-report.h"
 #include "hw/loader.h"
 #include "qemu/cutils.h"
+#include "elf.h"
 
 #define BIOS_FILENAME "ppc405_rom.bin"
 #define BIOS_SIZE (2 * MiB)
@@ -136,25 +137,101 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 }
 
+/*
+ * CPU reset handler when booting directly from a loaded kernel
+ */
+static struct boot_info {
+    uint32_t entry;
+    uint32_t bdloc;
+    uint32_t initrd_base;
+    uint32_t initrd_size;
+    uint32_t cmdline_base;
+    uint32_t cmdline_size;
+} boot_info;
+
+static void main_cpu_reset(void *opaque)
+{
+    PowerPCCPU *cpu = opaque;
+    CPUPPCState *env = &cpu->env;
+    struct boot_info *bi = env->load_info;
+
+    cpu_reset(CPU(cpu));
+
+    /* stack: top of sram */
+    env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8;
+
+    /* Tune our boot state */
+    env->gpr[3] = bi->bdloc;
+    env->gpr[4] = bi->initrd_base;
+    env->gpr[5] = bi->initrd_base + bi->initrd_size;
+    env->gpr[6] = bi->cmdline_base;
+    env->gpr[7] = bi->cmdline_size;
+
+    env->nip = bi->entry;
+}
+
+static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
+{
+    CPUPPCState *env = &cpu->env;
+    hwaddr boot_entry;
+    hwaddr kernel_base;
+    int kernel_size;
+    hwaddr initrd_base;
+    int initrd_size;
+    ram_addr_t bdloc;
+    int len;
+
+    bdloc = ppc405_set_bootinfo(env, machine->ram_size);
+    boot_info.bdloc = bdloc;
+
+    kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL,
+                           &boot_entry, &kernel_base, NULL, NULL,
+                           1, PPC_ELF_MACHINE, 0, 0);
+    if (kernel_size < 0) {
+        error_report("Could not load kernel '%s' : %s",
+                     machine->kernel_filename, load_elf_strerror(kernel_size));
+        exit(1);
+    }
+    boot_info.entry = boot_entry;
+
+    /* load initrd */
+    if (machine->initrd_filename) {
+        initrd_base = INITRD_LOAD_ADDR;
+        initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
+                                          machine->ram_size - initrd_base);
+        if (initrd_size < 0) {
+            error_report("could not load initial ram disk '%s'",
+                         machine->initrd_filename);
+            exit(1);
+        }
+
+        boot_info.initrd_base = initrd_base;
+        boot_info.initrd_size = initrd_size;
+    }
+
+    if (machine->kernel_cmdline) {
+        len = strlen(machine->kernel_cmdline);
+        bdloc -= ((len + 255) & ~255);
+        cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1);
+        boot_info.cmdline_base = bdloc;
+        boot_info.cmdline_size = bdloc + len;
+    }
+
+    /* Install our custom reset handler to start from Linux */
+    qemu_register_reset(main_cpu_reset, cpu);
+    env->load_info = &boot_info;
+}
+
 static void ref405ep_init(MachineState *machine)
 {
     MachineClass *mc = MACHINE_GET_CLASS(machine);
     const char *kernel_filename = machine->kernel_filename;
-    const char *kernel_cmdline = machine->kernel_cmdline;
-    const char *initrd_filename = machine->initrd_filename;
     PowerPCCPU *cpu;
-    CPUPPCState *env;
     DeviceState *dev;
     SysBusDevice *s;
     MemoryRegion *sram = g_new(MemoryRegion, 1);
-    ram_addr_t bdloc;
     MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
     hwaddr ram_bases[2], ram_sizes[2];
-    long bios_size = -1;
-    target_ulong kernel_base, initrd_base;
-    long kernel_size, initrd_size;
-    int linux_boot;
-    int len;
     MemoryRegion *sysmem = get_system_memory();
     DeviceState *uicdev;
 
@@ -176,7 +253,6 @@ static void ref405ep_init(MachineState *machine)
 
     cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
                         33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
-    env = &cpu->env;
 
     /* allocate SRAM */
     memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
@@ -187,6 +263,7 @@ static void ref405ep_init(MachineState *machine)
     if (machine->firmware) {
         MemoryRegion *bios = g_new(MemoryRegion, 1);
         g_autofree char *filename;
+        long bios_size;
 
         memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
                                &error_fatal);
@@ -217,54 +294,36 @@ static void ref405ep_init(MachineState *machine)
     s = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(s, &error_fatal);
     sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
-    /* Load kernel */
-    linux_boot = (kernel_filename != NULL);
-    if (linux_boot) {
-        bdloc = ppc405_set_bootinfo(env, machine->ram_size);
-        env->gpr[3] = bdloc;
+
+    /* Load kernel and initrd using U-Boot images */
+    if (kernel_filename && machine->firmware) {
+        target_ulong kernel_base, initrd_base;
+        long kernel_size, initrd_size;
+
         kernel_base = KERNEL_LOAD_ADDR;
-        /* now we can load the kernel */
         kernel_size = load_image_targphys(kernel_filename, kernel_base,
                                           machine->ram_size - kernel_base);
         if (kernel_size < 0) {
             error_report("could not load kernel '%s'", kernel_filename);
             exit(1);
         }
-        printf("Load kernel size %ld at " TARGET_FMT_lx,
-               kernel_size, kernel_base);
+
         /* load initrd */
-        if (initrd_filename) {
+        if (machine->initrd_filename) {
             initrd_base = INITRD_LOAD_ADDR;
-            initrd_size = load_image_targphys(initrd_filename, initrd_base,
+            initrd_size = load_image_targphys(machine->initrd_filename,
+                                              initrd_base,
                                               machine->ram_size - initrd_base);
             if (initrd_size < 0) {
                 error_report("could not load initial ram disk '%s'",
-                             initrd_filename);
+                             machine->initrd_filename);
                 exit(1);
             }
-        } else {
-            initrd_base = 0;
-            initrd_size = 0;
-        }
-        env->gpr[4] = initrd_base;
-        env->gpr[5] = initrd_size;
-        if (kernel_cmdline != NULL) {
-            len = strlen(kernel_cmdline);
-            bdloc -= ((len + 255) & ~255);
-            cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
-            env->gpr[6] = bdloc;
-            env->gpr[7] = bdloc + len;
-        } else {
-            env->gpr[6] = 0;
-            env->gpr[7] = 0;
         }
-        env->nip = KERNEL_LOAD_ADDR;
-    } else {
-        kernel_base = 0;
-        kernel_size = 0;
-        initrd_base = 0;
-        initrd_size = 0;
-        bdloc = 0;
+
+    /* Load ELF kernel and rootfs.cpio */
+    } else if (kernel_filename && !machine->firmware) {
+        boot_from_kernel(machine, cpu);
     }
 }
 
-- 
2.31.1

[PATCH 12/15] ppc/ppc405: Change default PLL values at reset

[Cédric Le Goater]

These values are computed and updated by U-Boot at startup. Use them
as defaults to improve direct Linux boot.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405_uc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 303af584443d..2a1e2d71b08b 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1381,9 +1381,9 @@ static void ppc405ep_cpc_reset (void *opaque)
 
     cpc->boot = 0x00000010;     /* Boot from PCI - IIC EEPROM disabled */
     cpc->epctl = 0x00000000;
-    cpc->pllmr[0] = 0x00011010;
-    cpc->pllmr[1] = 0x40000000;
-    cpc->ucr = 0x00000000;
+    cpc->pllmr[0] = 0x00021002;
+    cpc->pllmr[1] = 0x80a552be;
+    cpc->ucr = 0x00004646;
     cpc->srr = 0x00040000;
     cpc->pci = 0x00000000;
     cpc->er = 0x00000000;
-- 
2.31.1

[PATCH 13/15] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information

[Cédric Le Goater]

The board information for the 405EP first appeared in commit 04f20795ac81
("Move PowerPC 405 specific definitions into a separate file ...")
An Ethernet address is a 6 byte number. Fix that.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 6fb8b41bbc77..83f156f585c8 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -57,7 +57,7 @@ struct ppc4xx_bd_info_t {
     uint32_t bi_plb_busfreq;
     uint32_t bi_pci_busfreq;
     uint8_t  bi_pci_enetaddr[6];
-    uint32_t bi_pci_enetaddr2[6];
+    uint8_t  bi_pci_enetaddr2[6]; /* PPC405EP specific */
     uint32_t bi_opbfreq;
     uint32_t bi_iic_fast[2];
 };
-- 
2.31.1

[PATCH 14/15] ppc/ppc405: Add update of bi_procfreq field

[Cédric Le Goater]

Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405_uc.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2a1e2d71b08b..ec97b22bd019 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -102,12 +102,13 @@ static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
     for (i = 0; i < 32; i++) {
         stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
     }
-    stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
-    stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
+    stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
+    stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
+    stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
     for (i = 0; i < 6; i++) {
-        stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+        stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
     }
-    n = 0x6A;
+    n = 0x70; /* includes 2 bytes hole */
     for (i = 0; i < 6; i++) {
         stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
     }
-- 
2.31.1

[PATCH 15/15] ppc/ppc405: Update U-Boot board information for hotfoot

[Cédric Le Goater]

When support for the ESTeem 195E (PPC405EP) SBC (hotfoot) board was
added to Linux, a different layout of U-Boot board information was
introduced because the FW of these boards was an ancient U-Boot
without dual ethernet support [1].

Change the QEMU PPC405 board information to match the hotfoot board
and let the ref405ep machine boot from Linux directly. Only the CPU
frequency is required.

This is brutal force. We could possibly add a machine option or a
ref405ep machine class to update the board information accordingly.

A similar change would be required in U-Boot. The alternative is to
change Linux.

[1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html

Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405_uc.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index ec97b22bd019..649bb2b0daf5 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -41,6 +41,49 @@
 #include "qapi/error.h"
 #include "trace.h"
 
+/*
+ * Linux hotfoot board information based on a production bootloader
+ * (u-boot 1.2.0.x) plus changes not upstream.
+ *
+ * https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
+ */
+struct linux_hotfoot_bd_info {
+    long unsigned int          bi_memstart;          /*     0     4 */
+    long unsigned int          bi_memsize;           /*     4     4 */
+    long unsigned int          bi_flashstart;        /*     8     4 */
+    long unsigned int          bi_flashsize;         /*    12     4 */
+    long unsigned int          bi_flashoffset;       /*    16     4 */
+    long unsigned int          bi_sramstart;         /*    20     4 */
+    long unsigned int          bi_sramsize;          /*    24     4 */
+    long unsigned int          bi_bootflags;         /*    28     4 */
+    long unsigned int          bi_ip_addr;           /*    32     4 */
+    unsigned char              bi_enetaddr[6];       /*    36     6 */
+    unsigned char              bi_enet1addr[6];      /*    42     6 */
+    short unsigned int         bi_ethspeed;          /*    48     2 */
+    long unsigned int          bi_intfreq;           /*    52     4 */
+    long unsigned int          bi_busfreq;           /*    56     4 */
+    long unsigned int          bi_baudrate;          /*    60     4 */
+    unsigned char              bi_s_version[4];      /*    64     4 */
+    unsigned char              bi_r_version[32];     /*    68    32 */
+    unsigned int               bi_procfreq;          /*   100     4 */
+    unsigned int               bi_plb_busfreq;       /*   104     4 */
+    unsigned int               bi_pci_busfreq;       /*   108     4 */
+    unsigned char              bi_pci_enetaddr[6];   /*   112     6 */
+    unsigned int               bi_pllouta_freq;      /*   120     4 */
+    int                        bi_phynum[2];         /*   124     8 */
+    int                        bi_phymode[2];        /*   132     8 */
+    unsigned int               bi_opbfreq;           /*   140     4 */
+    int                        bi_iic_fast[2];       /*   144     8 */
+};
+
+static void ppc405_fixup_bootinfo(CPUState *cs, ppc4xx_bd_info_t *bd,
+                                  ram_addr_t bdloc)
+{
+    stl_be_phys(cs->as,
+                bdloc + offsetof(struct linux_hotfoot_bd_info, bi_procfreq),
+                bd->bi_procfreq);
+}
+
 static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
                                         ram_addr_t ram_size)
 {
@@ -119,6 +162,8 @@ static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
         n += 4;
     }
 
+    ppc405_fixup_bootinfo(cs, bd, bdloc);
+
     return bdloc;
 }
 
-- 
2.31.1

Re: [PATCH 03/15] ppc: Add trace-events for DCR accesses

[Philippe Mathieu-Daudé]

On 12/6/21 11:37, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/ppc/ppc.c        | 2 ++
>  hw/ppc/trace-events | 3 +++
>  2 files changed, 5 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH 05/15] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo()

[Philippe Mathieu-Daudé]

On 12/6/21 11:37, Cédric Le Goater wrote:
> It was introduced in commit b8d3f5d12642 ("Add flags to support
> PowerPC 405 bootinfos variations.") but since its value has always
> been set to '1'.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/ppc/ppc405.h        | 3 +--
>  hw/ppc/ppc405_boards.c | 2 +-
>  hw/ppc/ppc405_uc.c     | 8 +++-----
>  3 files changed, 5 insertions(+), 8 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH 07/15] ppc/ppc405: Add some address space definitions

[Philippe Mathieu-Daudé]

On 12/6/21 11:37, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/ppc/ppc405.h        |  7 +++++++
>  hw/ppc/ppc405_boards.c | 16 +++++++---------
>  2 files changed, 14 insertions(+), 9 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [PATCH 13/15] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information

[Philippe Mathieu-Daudé]

On 12/6/21 11:37, Cédric Le Goater wrote:
> The board information for the 405EP first appeared in commit 04f20795ac81
> ("Move PowerPC 405 specific definitions into a separate file ...")
> An Ethernet address is a 6 byte number. Fix that.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/ppc/ppc405.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 6fb8b41bbc77..83f156f585c8 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -57,7 +57,7 @@ struct ppc4xx_bd_info_t {
>      uint32_t bi_plb_busfreq;
>      uint32_t bi_pci_busfreq;
>      uint8_t  bi_pci_enetaddr[6];
> -    uint32_t bi_pci_enetaddr2[6];
> +    uint8_t  bi_pci_enetaddr2[6]; /* PPC405EP specific */

Also eventually 6 -> ETH_ALEN from "net/net.h".

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

>      uint32_t bi_opbfreq;
>      uint32_t bi_iic_fast[2];
>  };
> 

Re: [PATCH 15/15] ppc/ppc405: Update U-Boot board information for hotfoot

[Philippe Mathieu-Daudé]

On 12/6/21 11:37, Cédric Le Goater wrote:
> When support for the ESTeem 195E (PPC405EP) SBC (hotfoot) board was
> added to Linux, a different layout of U-Boot board information was
> introduced because the FW of these boards was an ancient U-Boot
> without dual ethernet support [1].
> 
> Change the QEMU PPC405 board information to match the hotfoot board
> and let the ref405ep machine boot from Linux directly. Only the CPU
> frequency is required.
> 
> This is brutal force. We could possibly add a machine option or a
> ref405ep machine class to update the board information accordingly.
> 
> A similar change would be required in U-Boot. The alternative is to
> change Linux.
> 
> [1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
> 
> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/ppc/ppc405_uc.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index ec97b22bd019..649bb2b0daf5 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -41,6 +41,49 @@
>  #include "qapi/error.h"
>  #include "trace.h"
>  
> +/*
> + * Linux hotfoot board information based on a production bootloader
> + * (u-boot 1.2.0.x) plus changes not upstream.
> + *
> + * https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
> + */
> +struct linux_hotfoot_bd_info {
> +    long unsigned int          bi_memstart;          /*     0     4 */
> +    long unsigned int          bi_memsize;           /*     4     4 */
> +    long unsigned int          bi_flashstart;        /*     8     4 */
> +    long unsigned int          bi_flashsize;         /*    12     4 */
> +    long unsigned int          bi_flashoffset;       /*    16     4 */
> +    long unsigned int          bi_sramstart;         /*    20     4 */
> +    long unsigned int          bi_sramsize;          /*    24     4 */
> +    long unsigned int          bi_bootflags;         /*    28     4 */
> +    long unsigned int          bi_ip_addr;           /*    32     4 */
> +    unsigned char              bi_enetaddr[6];       /*    36     6 */
> +    unsigned char              bi_enet1addr[6];      /*    42     6 */
> +    short unsigned int         bi_ethspeed;          /*    48     2 */
> +    long unsigned int          bi_intfreq;           /*    52     4 */
> +    long unsigned int          bi_busfreq;           /*    56     4 */
> +    long unsigned int          bi_baudrate;          /*    60     4 */
> +    unsigned char              bi_s_version[4];      /*    64     4 */
> +    unsigned char              bi_r_version[32];     /*    68    32 */
> +    unsigned int               bi_procfreq;          /*   100     4 */
> +    unsigned int               bi_plb_busfreq;       /*   104     4 */
> +    unsigned int               bi_pci_busfreq;       /*   108     4 */
> +    unsigned char              bi_pci_enetaddr[6];   /*   112     6 */
> +    unsigned int               bi_pllouta_freq;      /*   120     4 */
> +    int                        bi_phynum[2];         /*   124     8 */
> +    int                        bi_phymode[2];        /*   132     8 */
> +    unsigned int               bi_opbfreq;           /*   140     4 */
> +    int                        bi_iic_fast[2];       /*   144     8 */
> +};

Why not use <stdint.h> types?

Re: [PATCH 15/15] ppc/ppc405: Update U-Boot board information for hotfoot

[Cédric Le Goater]

On 12/6/21 14:27, Philippe Mathieu-Daudé wrote:
> On 12/6/21 11:37, Cédric Le Goater wrote:
>> When support for the ESTeem 195E (PPC405EP) SBC (hotfoot) board was
>> added to Linux, a different layout of U-Boot board information was
>> introduced because the FW of these boards was an ancient U-Boot
>> without dual ethernet support [1].
>>
>> Change the QEMU PPC405 board information to match the hotfoot board
>> and let the ref405ep machine boot from Linux directly. Only the CPU
>> frequency is required.
>>
>> This is brutal force. We could possibly add a machine option or a
>> ref405ep machine class to update the board information accordingly.
>>
>> A similar change would be required in U-Boot. The alternative is to
>> change Linux.
>>
>> [1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
>>
>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>   hw/ppc/ppc405_uc.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 45 insertions(+)
>>
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index ec97b22bd019..649bb2b0daf5 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -41,6 +41,49 @@
>>   #include "qapi/error.h"
>>   #include "trace.h"
>>   
>> +/*
>> + * Linux hotfoot board information based on a production bootloader
>> + * (u-boot 1.2.0.x) plus changes not upstream.
>> + *
>> + * https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
>> + */
>> +struct linux_hotfoot_bd_info {
>> +    long unsigned int          bi_memstart;          /*     0     4 */
>> +    long unsigned int          bi_memsize;           /*     4     4 */
>> +    long unsigned int          bi_flashstart;        /*     8     4 */
>> +    long unsigned int          bi_flashsize;         /*    12     4 */
>> +    long unsigned int          bi_flashoffset;       /*    16     4 */
>> +    long unsigned int          bi_sramstart;         /*    20     4 */
>> +    long unsigned int          bi_sramsize;          /*    24     4 */
>> +    long unsigned int          bi_bootflags;         /*    28     4 */
>> +    long unsigned int          bi_ip_addr;           /*    32     4 */
>> +    unsigned char              bi_enetaddr[6];       /*    36     6 */
>> +    unsigned char              bi_enet1addr[6];      /*    42     6 */
>> +    short unsigned int         bi_ethspeed;          /*    48     2 */
>> +    long unsigned int          bi_intfreq;           /*    52     4 */
>> +    long unsigned int          bi_busfreq;           /*    56     4 */
>> +    long unsigned int          bi_baudrate;          /*    60     4 */
>> +    unsigned char              bi_s_version[4];      /*    64     4 */
>> +    unsigned char              bi_r_version[32];     /*    68    32 */
>> +    unsigned int               bi_procfreq;          /*   100     4 */
>> +    unsigned int               bi_plb_busfreq;       /*   104     4 */
>> +    unsigned int               bi_pci_busfreq;       /*   108     4 */
>> +    unsigned char              bi_pci_enetaddr[6];   /*   112     6 */
>> +    unsigned int               bi_pllouta_freq;      /*   120     4 */
>> +    int                        bi_phynum[2];         /*   124     8 */
>> +    int                        bi_phymode[2];        /*   132     8 */
>> +    unsigned int               bi_opbfreq;           /*   140     4 */
>> +    int                        bi_iic_fast[2];       /*   144     8 */
>> +};
> 
> Why not use <stdint.h> types?

sure.

I am waiting for some feedback on this hack updating the in-memory
board information. I have the feeling that a new 405 machine
is required for this kernel :/

Thanks,

C.

Re: [PATCH 15/15] ppc/ppc405: Update U-Boot board information for hotfoot

[Thomas Huth]

On 06/12/2021 14.37, Cédric Le Goater wrote:
> On 12/6/21 14:27, Philippe Mathieu-Daudé wrote:
>> On 12/6/21 11:37, Cédric Le Goater wrote:
>>> When support for the ESTeem 195E (PPC405EP) SBC (hotfoot) board was
>>> added to Linux, a different layout of U-Boot board information was
>>> introduced because the FW of these boards was an ancient U-Boot
>>> without dual ethernet support [1].
>>>
>>> Change the QEMU PPC405 board information to match the hotfoot board
>>> and let the ref405ep machine boot from Linux directly. Only the CPU
>>> frequency is required.
>>>
>>> This is brutal force. We could possibly add a machine option or a
>>> ref405ep machine class to update the board information accordingly.
>>>
>>> A similar change would be required in U-Boot. The alternative is to
>>> change Linux.
>>>
>>> [1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
>>>
>>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>> ---
>>>   hw/ppc/ppc405_uc.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 45 insertions(+)
>>>
>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>> index ec97b22bd019..649bb2b0daf5 100644
>>> --- a/hw/ppc/ppc405_uc.c
>>> +++ b/hw/ppc/ppc405_uc.c
>>> @@ -41,6 +41,49 @@
>>>   #include "qapi/error.h"
>>>   #include "trace.h"
>>> +/*
>>> + * Linux hotfoot board information based on a production bootloader
>>> + * (u-boot 1.2.0.x) plus changes not upstream.
>>> + *
>>> + * https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
>>> + */
>>> +struct linux_hotfoot_bd_info {
>>> +    long unsigned int          bi_memstart;          /*     0     4 */
>>> +    long unsigned int          bi_memsize;           /*     4     4 */
>>> +    long unsigned int          bi_flashstart;        /*     8     4 */
>>> +    long unsigned int          bi_flashsize;         /*    12     4 */
>>> +    long unsigned int          bi_flashoffset;       /*    16     4 */
>>> +    long unsigned int          bi_sramstart;         /*    20     4 */
>>> +    long unsigned int          bi_sramsize;          /*    24     4 */
>>> +    long unsigned int          bi_bootflags;         /*    28     4 */
>>> +    long unsigned int          bi_ip_addr;           /*    32     4 */
>>> +    unsigned char              bi_enetaddr[6];       /*    36     6 */
>>> +    unsigned char              bi_enet1addr[6];      /*    42     6 */
>>> +    short unsigned int         bi_ethspeed;          /*    48     2 */
>>> +    long unsigned int          bi_intfreq;           /*    52     4 */
>>> +    long unsigned int          bi_busfreq;           /*    56     4 */
>>> +    long unsigned int          bi_baudrate;          /*    60     4 */
>>> +    unsigned char              bi_s_version[4];      /*    64     4 */
>>> +    unsigned char              bi_r_version[32];     /*    68    32 */
>>> +    unsigned int               bi_procfreq;          /*   100     4 */
>>> +    unsigned int               bi_plb_busfreq;       /*   104     4 */
>>> +    unsigned int               bi_pci_busfreq;       /*   108     4 */
>>> +    unsigned char              bi_pci_enetaddr[6];   /*   112     6 */
>>> +    unsigned int               bi_pllouta_freq;      /*   120     4 */
>>> +    int                        bi_phynum[2];         /*   124     8 */
>>> +    int                        bi_phymode[2];        /*   132     8 */
>>> +    unsigned int               bi_opbfreq;           /*   140     4 */
>>> +    int                        bi_iic_fast[2];       /*   144     8 */
>>> +};
>>
>> Why not use <stdint.h> types?
> 
> sure.
> 
> I am waiting for some feedback on this hack updating the in-memory
> board information. I have the feeling that a new 405 machine
> is required for this kernel :/

Yeah, it feels rather wrong to bend the ref405ep machine to match the 
hotfoot expectations of the kernel this way ... maybe it would be better to 
add an abstract qemu405 machine to the kernel?

  Thomas

Re: [PATCH 07/15] ppc/ppc405: Add some address space definitions

[BALATON Zoltan]

[-- Attachment #1: Type: text/plain, Size: 3596 bytes --]

On Mon, 6 Dec 2021, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h        |  7 +++++++
> hw/ppc/ppc405_boards.c | 16 +++++++---------
> 2 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index ad5f4026b5db..ea48c3626908 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -27,6 +27,13 @@
>
> #include "hw/ppc/ppc4xx.h"
>
> +#define PPC405EP_SDRAM_BASE 0x00000000
> +#define PPC405EP_NVRAM_BASE 0xF0000000
> +#define PPC405EP_FPGA_BASE  0xF0300000
> +#define PPC405EP_SRAM_BASE  0xFFF00000
> +#define PPC405EP_SRAM_SIZE  (512 * KiB)
> +#define PPC405EP_FLASH_BASE 0xFFF80000

Are these specific to the 405EP SoC itself or the board? Maybe it's better 
to put these in the board .c file and get rid of the ppc405.h later if 
there are no 405 specific parts needed. It's currently included also by 
440 machines because it has some functions re-used by them but those may 
be gone when QOM-ifying these eventually or could be moved to a ppc4xx.h 
instead. I've tried to make a distinction between 405, 440 and 4xx parts 
(the latter common to both) when adding sam460ex but did not finish this 
clean up completely.

Regards,
BALATON Zoltan

> +
> /* Bootinfo as set-up by u-boot */
> typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
> struct ppc4xx_bd_info_t {
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index fcdb6d4cf8a0..60dc81fa4880 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -154,7 +154,6 @@ static void ref405ep_init(MachineState *machine)
>     ram_addr_t bdloc;
>     MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
>     hwaddr ram_bases[2], ram_sizes[2];
> -    target_ulong sram_size;
>     long bios_size;
>     //int phy_addr = 0;
>     //static int phy_addr = 1;
> @@ -187,10 +186,9 @@ static void ref405ep_init(MachineState *machine)
>     env = &cpu->env;
>
>     /* allocate SRAM */
> -    sram_size = 512 * KiB;
> -    memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
> +    memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
>                            &error_fatal);
> -    memory_region_add_subregion(sysmem, 0xFFF00000, sram);
> +    memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
>     /* allocate and load BIOS */
> #ifdef USE_FLASH_BIOS
>     dinfo = drive_get(IF_PFLASH, 0, 0);
> @@ -230,24 +228,24 @@ static void ref405ep_init(MachineState *machine)
>         }
>     }
>     /* Register FPGA */
> -    ref405ep_fpga_init(sysmem, 0xF0300000);
> +    ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE);
>     /* Register NVRAM */
>     dev = qdev_new("sysbus-m48t08");
>     qdev_prop_set_int32(dev, "base-year", 1968);
>     s = SYS_BUS_DEVICE(dev);
>     sysbus_realize_and_unref(s, &error_fatal);
> -    sysbus_mmio_map(s, 0, 0xF0000000);
> +    sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
>     /* Load kernel */
>     linux_boot = (kernel_filename != NULL);
>     if (linux_boot) {
>         memset(&bd, 0, sizeof(bd));
> -        bd.bi_memstart = 0x00000000;
> +        bd.bi_memstart = PPC405EP_SDRAM_BASE;
>         bd.bi_memsize = machine->ram_size;
>         bd.bi_flashstart = -bios_size;
>         bd.bi_flashsize = -bios_size;
>         bd.bi_flashoffset = 0;
> -        bd.bi_sramstart = 0xFFF00000;
> -        bd.bi_sramsize = sram_size;
> +        bd.bi_sramstart = PPC405EP_SRAM_BASE;
> +        bd.bi_sramsize = PPC405EP_SRAM_SIZE;
>         bd.bi_bootflags = 0;
>         bd.bi_intfreq = 133333333;
>         bd.bi_busfreq = 33333333;
>

Re: [PATCH 11/15] ppc/ppc405: Fix boot from kernel

[BALATON Zoltan]

[-- Attachment #1: Type: text/plain, Size: 8477 bytes --]

On Mon, 6 Dec 2021, Cédric Le Goater wrote:
> The machine can already boot with kernel and initrd U-boot images if a
> firmware is loaded first. Adapt and improve the load sequence to let
> the machine boot directly from a Linux kernel ELF image and a usual
> initrd image if a firmware image is not provided. For that, install a
> custom CPU reset handler to setup the registers and to start the CPU
> from the Linux kernel entry point.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405_boards.c | 145 +++++++++++++++++++++++++++++------------
> 1 file changed, 102 insertions(+), 43 deletions(-)
>
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 71a652e2d846..3ae2b36373a5 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -41,6 +41,7 @@
> #include "qemu/error-report.h"
> #include "hw/loader.h"
> #include "qemu/cutils.h"
> +#include "elf.h"
>
> #define BIOS_FILENAME "ppc405_rom.bin"
> #define BIOS_SIZE (2 * MiB)
> @@ -136,25 +137,101 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
>     qemu_register_reset(&ref405ep_fpga_reset, fpga);
> }
>
> +/*
> + * CPU reset handler when booting directly from a loaded kernel
> + */
> +static struct boot_info {
> +    uint32_t entry;
> +    uint32_t bdloc;
> +    uint32_t initrd_base;
> +    uint32_t initrd_size;
> +    uint32_t cmdline_base;
> +    uint32_t cmdline_size;
> +} boot_info;
> +
> +static void main_cpu_reset(void *opaque)
> +{
> +    PowerPCCPU *cpu = opaque;
> +    CPUPPCState *env = &cpu->env;
> +    struct boot_info *bi = env->load_info;
> +
> +    cpu_reset(CPU(cpu));
> +
> +    /* stack: top of sram */
> +    env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8;
> +
> +    /* Tune our boot state */
> +    env->gpr[3] = bi->bdloc;
> +    env->gpr[4] = bi->initrd_base;
> +    env->gpr[5] = bi->initrd_base + bi->initrd_size;
> +    env->gpr[6] = bi->cmdline_base;
> +    env->gpr[7] = bi->cmdline_size;
> +
> +    env->nip = bi->entry;
> +}
> +
> +static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
> +{
> +    CPUPPCState *env = &cpu->env;
> +    hwaddr boot_entry;
> +    hwaddr kernel_base;
> +    int kernel_size;
> +    hwaddr initrd_base;
> +    int initrd_size;
> +    ram_addr_t bdloc;
> +    int len;
> +
> +    bdloc = ppc405_set_bootinfo(env, machine->ram_size);
> +    boot_info.bdloc = bdloc;
> +
> +    kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL,
> +                           &boot_entry, &kernel_base, NULL, NULL,
> +                           1, PPC_ELF_MACHINE, 0, 0);
> +    if (kernel_size < 0) {
> +        error_report("Could not load kernel '%s' : %s",
> +                     machine->kernel_filename, load_elf_strerror(kernel_size));
> +        exit(1);
> +    }
> +    boot_info.entry = boot_entry;
> +
> +    /* load initrd */
> +    if (machine->initrd_filename) {
> +        initrd_base = INITRD_LOAD_ADDR;
> +        initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
> +                                          machine->ram_size - initrd_base);
> +        if (initrd_size < 0) {
> +            error_report("could not load initial ram disk '%s'",
> +                         machine->initrd_filename);
> +            exit(1);
> +        }
> +
> +        boot_info.initrd_base = initrd_base;
> +        boot_info.initrd_size = initrd_size;
> +    }
> +
> +    if (machine->kernel_cmdline) {
> +        len = strlen(machine->kernel_cmdline);
> +        bdloc -= ((len + 255) & ~255);
> +        cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1);
> +        boot_info.cmdline_base = bdloc;
> +        boot_info.cmdline_size = bdloc + len;
> +    }
> +
> +    /* Install our custom reset handler to start from Linux */
> +    qemu_register_reset(main_cpu_reset, cpu);
> +    env->load_info = &boot_info;
> +}
> +
> static void ref405ep_init(MachineState *machine)
> {
>     MachineClass *mc = MACHINE_GET_CLASS(machine);
>     const char *kernel_filename = machine->kernel_filename;

You could also get rid of kernel_filename and use machine->kernel_filename 
instead like for the others below. It does not help readability especially 
if only this one is aliased in a local variable but not the others. 
(Getting rid of these variables could be a separate patch in case that 
simpifies the actual change in this patch for easier review.)

Regards,
BALATON Zoltan

> -    const char *kernel_cmdline = machine->kernel_cmdline;
> -    const char *initrd_filename = machine->initrd_filename;
>     PowerPCCPU *cpu;
> -    CPUPPCState *env;
>     DeviceState *dev;
>     SysBusDevice *s;
>     MemoryRegion *sram = g_new(MemoryRegion, 1);
> -    ram_addr_t bdloc;
>     MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
>     hwaddr ram_bases[2], ram_sizes[2];
> -    long bios_size = -1;
> -    target_ulong kernel_base, initrd_base;
> -    long kernel_size, initrd_size;
> -    int linux_boot;
> -    int len;
>     MemoryRegion *sysmem = get_system_memory();
>     DeviceState *uicdev;
>
> @@ -176,7 +253,6 @@ static void ref405ep_init(MachineState *machine)
>
>     cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
>                         33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
> -    env = &cpu->env;
>
>     /* allocate SRAM */
>     memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
> @@ -187,6 +263,7 @@ static void ref405ep_init(MachineState *machine)
>     if (machine->firmware) {
>         MemoryRegion *bios = g_new(MemoryRegion, 1);
>         g_autofree char *filename;
> +        long bios_size;
>
>         memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
>                                &error_fatal);
> @@ -217,54 +294,36 @@ static void ref405ep_init(MachineState *machine)
>     s = SYS_BUS_DEVICE(dev);
>     sysbus_realize_and_unref(s, &error_fatal);
>     sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
> -    /* Load kernel */
> -    linux_boot = (kernel_filename != NULL);
> -    if (linux_boot) {
> -        bdloc = ppc405_set_bootinfo(env, machine->ram_size);
> -        env->gpr[3] = bdloc;
> +
> +    /* Load kernel and initrd using U-Boot images */
> +    if (kernel_filename && machine->firmware) {
> +        target_ulong kernel_base, initrd_base;
> +        long kernel_size, initrd_size;
> +
>         kernel_base = KERNEL_LOAD_ADDR;
> -        /* now we can load the kernel */
>         kernel_size = load_image_targphys(kernel_filename, kernel_base,
>                                           machine->ram_size - kernel_base);
>         if (kernel_size < 0) {
>             error_report("could not load kernel '%s'", kernel_filename);
>             exit(1);
>         }
> -        printf("Load kernel size %ld at " TARGET_FMT_lx,
> -               kernel_size, kernel_base);
> +
>         /* load initrd */
> -        if (initrd_filename) {
> +        if (machine->initrd_filename) {
>             initrd_base = INITRD_LOAD_ADDR;
> -            initrd_size = load_image_targphys(initrd_filename, initrd_base,
> +            initrd_size = load_image_targphys(machine->initrd_filename,
> +                                              initrd_base,
>                                               machine->ram_size - initrd_base);
>             if (initrd_size < 0) {
>                 error_report("could not load initial ram disk '%s'",
> -                             initrd_filename);
> +                             machine->initrd_filename);
>                 exit(1);
>             }
> -        } else {
> -            initrd_base = 0;
> -            initrd_size = 0;
> -        }
> -        env->gpr[4] = initrd_base;
> -        env->gpr[5] = initrd_size;
> -        if (kernel_cmdline != NULL) {
> -            len = strlen(kernel_cmdline);
> -            bdloc -= ((len + 255) & ~255);
> -            cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
> -            env->gpr[6] = bdloc;
> -            env->gpr[7] = bdloc + len;
> -        } else {
> -            env->gpr[6] = 0;
> -            env->gpr[7] = 0;
>         }
> -        env->nip = KERNEL_LOAD_ADDR;
> -    } else {
> -        kernel_base = 0;
> -        kernel_size = 0;
> -        initrd_base = 0;
> -        initrd_size = 0;
> -        bdloc = 0;
> +
> +    /* Load ELF kernel and rootfs.cpio */
> +    } else if (kernel_filename && !machine->firmware) {
> +        boot_from_kernel(machine, cpu);
>     }
> }
>
>

Re: [PATCH 15/15] ppc/ppc405: Update U-Boot board information for hotfoot

[Cédric Le Goater]

On 12/6/21 14:40, Thomas Huth wrote:
> On 06/12/2021 14.37, Cédric Le Goater wrote:
>> On 12/6/21 14:27, Philippe Mathieu-Daudé wrote:
>>> On 12/6/21 11:37, Cédric Le Goater wrote:
>>>> When support for the ESTeem 195E (PPC405EP) SBC (hotfoot) board was
>>>> added to Linux, a different layout of U-Boot board information was
>>>> introduced because the FW of these boards was an ancient U-Boot
>>>> without dual ethernet support [1].
>>>>
>>>> Change the QEMU PPC405 board information to match the hotfoot board
>>>> and let the ref405ep machine boot from Linux directly. Only the CPU
>>>> frequency is required.
>>>>
>>>> This is brutal force. We could possibly add a machine option or a
>>>> ref405ep machine class to update the board information accordingly.
>>>>
>>>> A similar change would be required in U-Boot. The alternative is to
>>>> change Linux.
>>>>
>>>> [1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
>>>>
>>>> Cc: Christophe Leroy <christophe.leroy@c-s.fr>
>>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>>>> ---
>>>>   hw/ppc/ppc405_uc.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>>>>   1 file changed, 45 insertions(+)
>>>>
>>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>>> index ec97b22bd019..649bb2b0daf5 100644
>>>> --- a/hw/ppc/ppc405_uc.c
>>>> +++ b/hw/ppc/ppc405_uc.c
>>>> @@ -41,6 +41,49 @@
>>>>   #include "qapi/error.h"
>>>>   #include "trace.h"
>>>> +/*
>>>> + * Linux hotfoot board information based on a production bootloader
>>>> + * (u-boot 1.2.0.x) plus changes not upstream.
>>>> + *
>>>> + * https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
>>>> + */
>>>> +struct linux_hotfoot_bd_info {
>>>> +    long unsigned int          bi_memstart;          /*     0     4 */
>>>> +    long unsigned int          bi_memsize;           /*     4     4 */
>>>> +    long unsigned int          bi_flashstart;        /*     8     4 */
>>>> +    long unsigned int          bi_flashsize;         /*    12     4 */
>>>> +    long unsigned int          bi_flashoffset;       /*    16     4 */
>>>> +    long unsigned int          bi_sramstart;         /*    20     4 */
>>>> +    long unsigned int          bi_sramsize;          /*    24     4 */
>>>> +    long unsigned int          bi_bootflags;         /*    28     4 */
>>>> +    long unsigned int          bi_ip_addr;           /*    32     4 */
>>>> +    unsigned char              bi_enetaddr[6];       /*    36     6 */
>>>> +    unsigned char              bi_enet1addr[6];      /*    42     6 */
>>>> +    short unsigned int         bi_ethspeed;          /*    48     2 */
>>>> +    long unsigned int          bi_intfreq;           /*    52     4 */
>>>> +    long unsigned int          bi_busfreq;           /*    56     4 */
>>>> +    long unsigned int          bi_baudrate;          /*    60     4 */
>>>> +    unsigned char              bi_s_version[4];      /*    64     4 */
>>>> +    unsigned char              bi_r_version[32];     /*    68    32 */
>>>> +    unsigned int               bi_procfreq;          /*   100     4 */
>>>> +    unsigned int               bi_plb_busfreq;       /*   104     4 */
>>>> +    unsigned int               bi_pci_busfreq;       /*   108     4 */
>>>> +    unsigned char              bi_pci_enetaddr[6];   /*   112     6 */
>>>> +    unsigned int               bi_pllouta_freq;      /*   120     4 */
>>>> +    int                        bi_phynum[2];         /*   124     8 */
>>>> +    int                        bi_phymode[2];        /*   132     8 */
>>>> +    unsigned int               bi_opbfreq;           /*   140     4 */
>>>> +    int                        bi_iic_fast[2];       /*   144     8 */
>>>> +};
>>>
>>> Why not use <stdint.h> types?
>>
>> sure.
>>
>> I am waiting for some feedback on this hack updating the in-memory
>> board information. I have the feeling that a new 405 machine
>> is required for this kernel :/
> 
> Yeah, it feels rather wrong to bend the ref405ep machine to match the hotfoot expectations of the kernel this way ... maybe it would be better to add an abstract qemu405 machine to the kernel?

Yes. I prepared that but then I realized that the QEMU board information
layout assigned (luckily) the CPU clock to 33 Mhz and not 0 like U-Boot
did. This structure is completely out of sync :/

Anyhow, the ref405ep machine can boot with a hotfoot Linux kernel without
having to patch the board information. We might merge a ref405ep-hotfoot
machine for the sake of clarity since it is a small and well contained
extension and the machine boots faster.

We still have a user space issue when forking processes. But that's
Christophe's turf.

Thanks,

C.
  

Re: [PATCH 07/15] ppc/ppc405: Add some address space definitions

[Cédric Le Goater]

On 12/6/21 16:05, BALATON Zoltan wrote:
> On Mon, 6 Dec 2021, Cédric Le Goater wrote:
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405.h        |  7 +++++++
>> hw/ppc/ppc405_boards.c | 16 +++++++---------
>> 2 files changed, 14 insertions(+), 9 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index ad5f4026b5db..ea48c3626908 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -27,6 +27,13 @@
>>
>> #include "hw/ppc/ppc4xx.h"
>>
>> +#define PPC405EP_SDRAM_BASE 0x00000000
>> +#define PPC405EP_NVRAM_BASE 0xF0000000
>> +#define PPC405EP_FPGA_BASE  0xF0300000
>> +#define PPC405EP_SRAM_BASE  0xFFF00000
>> +#define PPC405EP_SRAM_SIZE  (512 * KiB)
>> +#define PPC405EP_FLASH_BASE 0xFFF80000
> 
> Are these specific to the 405EP SoC itself or the board? 

yes.

> Maybe it's better to put these in the board .c file and get rid of the ppc405.h later if there are no 405 specific parts needed. 

Not yet. But I am moving to the ppc405_uc.c file parts related to
the board information and ppc405_uc.c is really 405 specific. See
other patches.

> It's currently included also by 440 machines because it has some functions re-used by them 

Indeed in hw/ppc/sam460ex.c:

	ppc405_ebc_init(env)

> but those may be gone when QOM-ifying these eventually 

QOM-ifying the 405 devices should be straight forward for most.
We can do a few to cleanup the dependencies like above. All models
will need a CPU link for the dcr handlers.

> or could be moved to a ppc4xx.h instead. 

yes. that would be fine but not necessary if we QOM-ify some parts.

> I've tried to make a distinction between 405, 440 and 4xx parts (the latter common to both) when adding sam460ex but did not finish this clean up completely.

I have a little patch removing all the printfs I will send soon.
Then we can move some code around.

I put some efforts on the 405 because it has been dead for so long
and at some point we need to identify dead code. It's alive now,
4.16 boots, we could even add PCI and network but first, user space
needs some care.

Thanks,

C.
  

Re: [PATCH 11/15] ppc/ppc405: Fix boot from kernel

[Cédric Le Goater]

On 12/6/21 16:16, BALATON Zoltan wrote:
> On Mon, 6 Dec 2021, Cédric Le Goater wrote:
>> The machine can already boot with kernel and initrd U-boot images if a
>> firmware is loaded first. Adapt and improve the load sequence to let
>> the machine boot directly from a Linux kernel ELF image and a usual
>> initrd image if a firmware image is not provided. For that, install a
>> custom CPU reset handler to setup the registers and to start the CPU
>> from the Linux kernel entry point.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> hw/ppc/ppc405_boards.c | 145 +++++++++++++++++++++++++++++------------
>> 1 file changed, 102 insertions(+), 43 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 71a652e2d846..3ae2b36373a5 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -41,6 +41,7 @@
>> #include "qemu/error-report.h"
>> #include "hw/loader.h"
>> #include "qemu/cutils.h"
>> +#include "elf.h"
>>
>> #define BIOS_FILENAME "ppc405_rom.bin"
>> #define BIOS_SIZE (2 * MiB)
>> @@ -136,25 +137,101 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
>>     qemu_register_reset(&ref405ep_fpga_reset, fpga);
>> }
>>
>> +/*
>> + * CPU reset handler when booting directly from a loaded kernel
>> + */
>> +static struct boot_info {
>> +    uint32_t entry;
>> +    uint32_t bdloc;
>> +    uint32_t initrd_base;
>> +    uint32_t initrd_size;
>> +    uint32_t cmdline_base;
>> +    uint32_t cmdline_size;
>> +} boot_info;
>> +
>> +static void main_cpu_reset(void *opaque)
>> +{
>> +    PowerPCCPU *cpu = opaque;
>> +    CPUPPCState *env = &cpu->env;
>> +    struct boot_info *bi = env->load_info;
>> +
>> +    cpu_reset(CPU(cpu));
>> +
>> +    /* stack: top of sram */
>> +    env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8;
>> +
>> +    /* Tune our boot state */
>> +    env->gpr[3] = bi->bdloc;
>> +    env->gpr[4] = bi->initrd_base;
>> +    env->gpr[5] = bi->initrd_base + bi->initrd_size;
>> +    env->gpr[6] = bi->cmdline_base;
>> +    env->gpr[7] = bi->cmdline_size;
>> +
>> +    env->nip = bi->entry;
>> +}
>> +
>> +static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
>> +{
>> +    CPUPPCState *env = &cpu->env;
>> +    hwaddr boot_entry;
>> +    hwaddr kernel_base;
>> +    int kernel_size;
>> +    hwaddr initrd_base;
>> +    int initrd_size;
>> +    ram_addr_t bdloc;
>> +    int len;
>> +
>> +    bdloc = ppc405_set_bootinfo(env, machine->ram_size);
>> +    boot_info.bdloc = bdloc;
>> +
>> +    kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL,
>> +                           &boot_entry, &kernel_base, NULL, NULL,
>> +                           1, PPC_ELF_MACHINE, 0, 0);
>> +    if (kernel_size < 0) {
>> +        error_report("Could not load kernel '%s' : %s",
>> +                     machine->kernel_filename, load_elf_strerror(kernel_size));
>> +        exit(1);
>> +    }
>> +    boot_info.entry = boot_entry;
>> +
>> +    /* load initrd */
>> +    if (machine->initrd_filename) {
>> +        initrd_base = INITRD_LOAD_ADDR;
>> +        initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
>> +                                          machine->ram_size - initrd_base);
>> +        if (initrd_size < 0) {
>> +            error_report("could not load initial ram disk '%s'",
>> +                         machine->initrd_filename);
>> +            exit(1);
>> +        }
>> +
>> +        boot_info.initrd_base = initrd_base;
>> +        boot_info.initrd_size = initrd_size;
>> +    }
>> +
>> +    if (machine->kernel_cmdline) {
>> +        len = strlen(machine->kernel_cmdline);
>> +        bdloc -= ((len + 255) & ~255);
>> +        cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1);
>> +        boot_info.cmdline_base = bdloc;
>> +        boot_info.cmdline_size = bdloc + len;
>> +    }
>> +
>> +    /* Install our custom reset handler to start from Linux */
>> +    qemu_register_reset(main_cpu_reset, cpu);
>> +    env->load_info = &boot_info;
>> +}
>> +
>> static void ref405ep_init(MachineState *machine)
>> {
>>     MachineClass *mc = MACHINE_GET_CLASS(machine);
>>     const char *kernel_filename = machine->kernel_filename;
> 
> You could also get rid of kernel_filename and use machine->kernel_filename instead like for the others below. It does not help readability especially if only this one is aliased in a local variable but not the others. (Getting rid of these variables could be a separate patch in case that simpifies the actual change in this patch for easier review.)

Yes. I did reshuffle the patchset a few times to make it clearer.
I agree that part is still a bit fuzzy. I will add your suggestion
in a v2.

Thanks,

C.


> 
> Regards,
> BALATON Zoltan
> 
>> -    const char *kernel_cmdline = machine->kernel_cmdline;
>> -    const char *initrd_filename = machine->initrd_filename;
>>     PowerPCCPU *cpu;
>> -    CPUPPCState *env;
>>     DeviceState *dev;
>>     SysBusDevice *s;
>>     MemoryRegion *sram = g_new(MemoryRegion, 1);
>> -    ram_addr_t bdloc;
>>     MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
>>     hwaddr ram_bases[2], ram_sizes[2];
>> -    long bios_size = -1;
>> -    target_ulong kernel_base, initrd_base;
>> -    long kernel_size, initrd_size;
>> -    int linux_boot;
>> -    int len;
>>     MemoryRegion *sysmem = get_system_memory();
>>     DeviceState *uicdev;
>>
>> @@ -176,7 +253,6 @@ static void ref405ep_init(MachineState *machine)
>>
>>     cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
>>                         33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
>> -    env = &cpu->env;
>>
>>     /* allocate SRAM */
>>     memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
>> @@ -187,6 +263,7 @@ static void ref405ep_init(MachineState *machine)
>>     if (machine->firmware) {
>>         MemoryRegion *bios = g_new(MemoryRegion, 1);
>>         g_autofree char *filename;
>> +        long bios_size;
>>
>>         memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
>>                                &error_fatal);
>> @@ -217,54 +294,36 @@ static void ref405ep_init(MachineState *machine)
>>     s = SYS_BUS_DEVICE(dev);
>>     sysbus_realize_and_unref(s, &error_fatal);
>>     sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
>> -    /* Load kernel */
>> -    linux_boot = (kernel_filename != NULL);
>> -    if (linux_boot) {
>> -        bdloc = ppc405_set_bootinfo(env, machine->ram_size);
>> -        env->gpr[3] = bdloc;
>> +
>> +    /* Load kernel and initrd using U-Boot images */
>> +    if (kernel_filename && machine->firmware) {
>> +        target_ulong kernel_base, initrd_base;
>> +        long kernel_size, initrd_size;
>> +
>>         kernel_base = KERNEL_LOAD_ADDR;
>> -        /* now we can load the kernel */
>>         kernel_size = load_image_targphys(kernel_filename, kernel_base,
>>                                           machine->ram_size - kernel_base);
>>         if (kernel_size < 0) {
>>             error_report("could not load kernel '%s'", kernel_filename);
>>             exit(1);
>>         }
>> -        printf("Load kernel size %ld at " TARGET_FMT_lx,
>> -               kernel_size, kernel_base);
>> +
>>         /* load initrd */
>> -        if (initrd_filename) {
>> +        if (machine->initrd_filename) {
>>             initrd_base = INITRD_LOAD_ADDR;
>> -            initrd_size = load_image_targphys(initrd_filename, initrd_base,
>> +            initrd_size = load_image_targphys(machine->initrd_filename,
>> +                                              initrd_base,
>>                                               machine->ram_size - initrd_base);
>>             if (initrd_size < 0) {
>>                 error_report("could not load initial ram disk '%s'",
>> -                             initrd_filename);
>> +                             machine->initrd_filename);
>>                 exit(1);
>>             }
>> -        } else {
>> -            initrd_base = 0;
>> -            initrd_size = 0;
>> -        }
>> -        env->gpr[4] = initrd_base;
>> -        env->gpr[5] = initrd_size;
>> -        if (kernel_cmdline != NULL) {
>> -            len = strlen(kernel_cmdline);
>> -            bdloc -= ((len + 255) & ~255);
>> -            cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
>> -            env->gpr[6] = bdloc;
>> -            env->gpr[7] = bdloc + len;
>> -        } else {
>> -            env->gpr[6] = 0;
>> -            env->gpr[7] = 0;
>>         }
>> -        env->nip = KERNEL_LOAD_ADDR;
>> -    } else {
>> -        kernel_base = 0;
>> -        kernel_size = 0;
>> -        initrd_base = 0;
>> -        initrd_size = 0;
>> -        bdloc = 0;
>> +
>> +    /* Load ELF kernel and rootfs.cpio */
>> +    } else if (kernel_filename && !machine->firmware) {
>> +        boot_from_kernel(machine, cpu);
>>     }
>> }
>>
>>

Re: [PATCH 00/15] ppc/ppc405: decade cleanup

[Cédric Le Goater]

On 12/6/21 11:36, Cédric Le Goater wrote:
> Hello,
> 
> The goal of these changes is to refresh the QEMU ref405ep machine and
> enable boot from a Linux kernel without relying on a U-Boot firmware.
> The reason for doing so is that we are unable to find a "ppc405_rom.bin"
> firmware image or a flash image for the 405EP machines.
> 
> Thomas fought is way through on a v2015.10 U-Boot and taihu defconfig
> and provided a compatible image available here :
> 
>   https://gitlab.com/huth/u-boot/-/tree/taihu/
> 
> With this image, QEMU reaches the U-Boot prompt (with a simple
> workaround in the SDRAM).
> 
> On the Linux side, the only available 405EP CPU board is the one for
> the ESTeem 195E (PPC405EP) SBC (hotfoot). It was added in 2009. The
> board information structure in Linux, in U-Boot and in QEMU are not in
> sync and the hotfoot board also adds its own flavor because the FW was
> an ancient U-Boot without dual ethernet support [1].
> 
> For this kernel to be loaded by the U-Boot image provided by Thomas,
> we either need to modify U-Boot or Linux. The same question arise for
> QEMU, see the last patch of this series which is controversial. Please
> advise !

Applied patch 1-14 to ppc-next.

I kept the hotfoot hack for later. We need to fix user space first.

Thanks,

C.

Re: [PATCH 00/15] ppc/ppc405: decade cleanup

[Christophe Leroy]

Le 15/12/2021 à 17:49, Cédric Le Goater a écrit :
> On 12/6/21 11:36, Cédric Le Goater wrote:
>> Hello,
>>
>> The goal of these changes is to refresh the QEMU ref405ep machine and
>> enable boot from a Linux kernel without relying on a U-Boot firmware.
>> The reason for doing so is that we are unable to find a "ppc405_rom.bin"
>> firmware image or a flash image for the 405EP machines.
>>
>> Thomas fought is way through on a v2015.10 U-Boot and taihu defconfig
>> and provided a compatible image available here :
>>
>>   https://gitlab.com/huth/u-boot/-/tree/taihu/
>>
>> With this image, QEMU reaches the U-Boot prompt (with a simple
>> workaround in the SDRAM).
>>
>> On the Linux side, the only available 405EP CPU board is the one for
>> the ESTeem 195E (PPC405EP) SBC (hotfoot). It was added in 2009. The
>> board information structure in Linux, in U-Boot and in QEMU are not in
>> sync and the hotfoot board also adds its own flavor because the FW was
>> an ancient U-Boot without dual ethernet support [1].
>>
>> For this kernel to be loaded by the U-Boot image provided by Thomas,
>> we either need to modify U-Boot or Linux. The same question arise for
>> QEMU, see the last patch of this series which is controversial. Please
>> advise !
> 
> Applied patch 1-14 to ppc-next.
> 
> I kept the hotfoot hack for later. We need to fix user space first.
> 


Don't know if this is the reason of our problems but I think there is 
something to investigate around timer interrupts:


/ # cat /proc/interrupts
            CPU0
  16:         68       UIC   1 Level     serial
LOC:          0   Local timer interrupts for timer event device
LOC:          0   Local timer interrupts for others
SPU:          0   Spurious interrupts
PMI:          0   Performance monitoring interrupts
MCE:          0   Machine check exceptions

Any idea what the problem can be ? How does QEMU generates timer 
interrupts ?

Christophe

Re: [PATCH 00/15] ppc/ppc405: decade cleanup

[Cédric Le Goater]

On 12/17/21 17:36, Christophe Leroy wrote:
> 
> 
> Le 15/12/2021 à 17:49, Cédric Le Goater a écrit :
>> On 12/6/21 11:36, Cédric Le Goater wrote:
>>> Hello,
>>>
>>> The goal of these changes is to refresh the QEMU ref405ep machine and
>>> enable boot from a Linux kernel without relying on a U-Boot firmware.
>>> The reason for doing so is that we are unable to find a "ppc405_rom.bin"
>>> firmware image or a flash image for the 405EP machines.
>>>
>>> Thomas fought is way through on a v2015.10 U-Boot and taihu defconfig
>>> and provided a compatible image available here :
>>>
>>>    https://gitlab.com/huth/u-boot/-/tree/taihu/
>>>
>>> With this image, QEMU reaches the U-Boot prompt (with a simple
>>> workaround in the SDRAM).
>>>
>>> On the Linux side, the only available 405EP CPU board is the one for
>>> the ESTeem 195E (PPC405EP) SBC (hotfoot). It was added in 2009. The
>>> board information structure in Linux, in U-Boot and in QEMU are not in
>>> sync and the hotfoot board also adds its own flavor because the FW was
>>> an ancient U-Boot without dual ethernet support [1].
>>>
>>> For this kernel to be loaded by the U-Boot image provided by Thomas,
>>> we either need to modify U-Boot or Linux. The same question arise for
>>> QEMU, see the last patch of this series which is controversial. Please
>>> advise !
>>
>> Applied patch 1-14 to ppc-next.
>>
>> I kept the hotfoot hack for later. We need to fix user space first.
>>
> 
> 
> Don't know if this is the reason of our problems but I think there is
> something to investigate around timer interrupts:
> 
> 
> / # cat /proc/interrupts
>              CPU0
>    16:         68       UIC   1 Level     serial
> LOC:          0   Local timer interrupts for timer event device
> LOC:          0   Local timer interrupts for others
> SPU:          0   Spurious interrupts
> PMI:          0   Performance monitoring interrupts
> MCE:          0   Machine check exceptions
> 
> Any idea what the problem can be ? How does QEMU generates timer
> interrupts ?

Indeed.

With some extra QEMU traces (-trace ppc4* -trace ppc_decr*), we can see :

ppc40x_timers_init frequency 33333333
ppc405_gpio_init offet 0xef600700
ppc4xx_gpt_init offet 0xef600000
ppc405ep_clocks_compute FBMUL 0xa 10
ppc405ep_clocks_compute FWDA 0x5 3
ppc405ep_clocks_compute CCDV 0x0 1
ppc405ep_clocks_compute CBDV 0x2 3
ppc405ep_clocks_compute OPDV 0x1 2
ppc405ep_clocks_compute EPDV 0x0 2
ppc405ep_clocks_compute MPDV 0x0 1
ppc405ep_clocks_compute PPDV 0x2 3
ppc405ep_clocks_compute U0DIV 0x46 70
ppc405ep_clocks_compute U1DIV 0x46 70
ppc405ep_clocks_setup Setup PPC405EP clocks - sysclk 33333333 VCO 999999990 PLL out 333333330 Hz
CPU 333333330 PLB 111111110 OPB 55555555 EBC 55555555 MAL 111111110 PCI 37037036 UART0 4761904 UART1 4761904

ppc40x_set_tb_clk new frequency 333333330

   ...

   clocksource: timebase mult[7800000] shift[24] registered
ppc40x_store_pit val 0x7fffffff
ppc4xx_pit_stop
ppc40x_store_pit val 0x82355
ppc4xx_pit_stop
   pid_max: default: 32768 minimum: 301


decrementer timer seems stop and so no decrementer exception. I suppose
this routine is in cause :


static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
{
     ppc40x_timer_t *ppc40x_timer;
     uint64_t now, next;

     ppc40x_timer = tb_env->opaque;
     if (ppc40x_timer->pit_reload <= 1 ||
         !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
         (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
         /* Stop PIT */
         trace_ppc4xx_pit_stop();
         timer_del(tb_env->decr_timer);
     } else {
         trace_ppc4xx_pit_start(ppc40x_timer->pit_reload);
         now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
         next = now + muldiv64(ppc40x_timer->pit_reload,
                               NANOSECONDS_PER_SECOND, tb_env->decr_freq);
         if (is_excp)
             next += tb_env->decr_next - now;
         if (next == now)
             next++;
         timer_mod(tb_env->decr_timer, next);
         tb_env->decr_next = next;
     }
}


C.

Re: [PATCH 00/15] ppc/ppc405: decade cleanup

[Cédric Le Goater]

>> Don't know if this is the reason of our problems but I think there is
>> something to investigate around timer interrupts:
>>
>>
>> / # cat /proc/interrupts
>>              CPU0
>>    16:         68       UIC   1 Level     serial
>> LOC:          0   Local timer interrupts for timer event device
>> LOC:          0   Local timer interrupts for others
>> SPU:          0   Spurious interrupts
>> PMI:          0   Performance monitoring interrupts
>> MCE:          0   Machine check exceptions
>>
>> Any idea what the problem can be ? How does QEMU generates timer
>> interrupts ?

The ppc405 timers were trashed by ddd1055b07fd ("PPC: booke timers").
I guess at the time, in 2011, there were no possible ways to test
regressions :/

This is addictive. I will look into it, I hope it's only a question
of adding back the TSR and TCR store helpers.

Thanks,

C.

Re: [PATCH 00/15] ppc/ppc405: decade cleanup

[Cédric Le Goater]

> 
> Don't know if this is the reason of our problems but I think there is
> something to investigate around timer interrupts:
> 
> 
> / # cat /proc/interrupts
>              CPU0
>    16:         68       UIC   1 Level     serial
> LOC:          0   Local timer interrupts for timer event device
> LOC:          0   Local timer interrupts for others
> SPU:          0   Spurious interrupts
> PMI:          0   Performance monitoring interrupts
> MCE:          0   Machine check exceptions
> 
> Any idea what the problem can be ? How does QEMU generates timer
> interrupts ?

I did some archeology and fixed the 405 timer (PIT). Please see commits in :

   https://github.com/legoater/qemu/commits/ppc405

but we are still getting segfaults. At some point /init tries to load from
fffffe04 which is obviously wrong.

Add -d int,mmu to have more info from QEMU internals.

I have gathered some info on this page :

   https://github.com/legoater/qemu/wiki/ref405ep

Thanks,

C.

Re: [PATCH 00/15] ppc/ppc405: decade cleanup

[Philippe Mathieu-Daudé]

On 12/20/21 09:33, Cédric Le Goater wrote:
>>
>> Don't know if this is the reason of our problems but I think there is
>> something to investigate around timer interrupts:
>>
>>
>> / # cat /proc/interrupts
>>              CPU0
>>    16:         68       UIC   1 Level     serial
>> LOC:          0   Local timer interrupts for timer event device
>> LOC:          0   Local timer interrupts for others
>> SPU:          0   Spurious interrupts
>> PMI:          0   Performance monitoring interrupts
>> MCE:          0   Machine check exceptions
>>
>> Any idea what the problem can be ? How does QEMU generates timer
>> interrupts ?
> 
> I did some archeology and fixed the 405 timer (PIT). Please see commits
> in :
> 
>   https://github.com/legoater/qemu/commits/ppc405
> 
> but we are still getting segfaults. At some point /init tries to load from
> fffffe04 which is obviously wrong.

Fetching an u32 value from a missing ROM?

> 
> Add -d int,mmu to have more info from QEMU internals.
> 
> I have gathered some info on this page :
> 
>   https://github.com/legoater/qemu/wiki/ref405ep
> 
> Thanks,
> 
> C.
> 

Re: [PATCH 00/15] ppc/ppc405: decade cleanup

[Cédric Le Goater]

On 12/20/21 19:07, Philippe Mathieu-Daudé wrote:
> On 12/20/21 09:33, Cédric Le Goater wrote:
>>>
>>> Don't know if this is the reason of our problems but I think there is
>>> something to investigate around timer interrupts:
>>>
>>>
>>> / # cat /proc/interrupts
>>>               CPU0
>>>     16:         68       UIC   1 Level     serial
>>> LOC:          0   Local timer interrupts for timer event device
>>> LOC:          0   Local timer interrupts for others
>>> SPU:          0   Spurious interrupts
>>> PMI:          0   Performance monitoring interrupts
>>> MCE:          0   Machine check exceptions
>>>
>>> Any idea what the problem can be ? How does QEMU generates timer
>>> interrupts ?
>>
>> I did some archeology and fixed the 405 timer (PIT). Please see commits
>> in :
>>
>>    https://github.com/legoater/qemu/commits/ppc405
>>
>> but we are still getting segfaults. At some point /init tries to load from
>> fffffe04 which is obviously wrong.
> 
> Fetching an u32 value from a missing ROM?


hmm, I don't think so. Here are some logs.

Thanks,

C.

....
mmu40x_get_physical_address: access granted b7bd6000 => 00000000005ba000 13 0

0xb7bd6744:  80dffff8  lwz      r6, -8(r31)
0xb7bd6748:  7ce63850  subf     r7, r6, r7
0xb7bd674c:  80a70008  lwz      r5, 8(r7)
0xb7bd6750:  7c843214  add      r4, r4, r6
0xb7bd6754:  8065000c  lwz      r3, 0xc(r5)
0xb7bd6758:  80c7000c  lwz      r6, 0xc(r7)
0xb7bd675c:  7c071800  cmpw     r7, r3
0xb7bd6760:  41a20008  beq      0xb7bd6768

ppcemb_tlb_check: TLB 14 address fffffe04 PID 3 <=> c0000000 ff000000 0 f
ppcemb_tlb_check: TLB 15 address fffffe04 PID 3 <=> c7000000 ff000000 0 f
ppcemb_tlb_check: TLB 16 address fffffe04 PID 3 <=> c1000000 ff000000 0 f
ppcemb_tlb_check: TLB 17 address fffffe04 PID 3 <=> b7bdc000 fffff000 2 d
ppcemb_tlb_check: TLB 19 address fffffe04 PID 3 <=> b7c30000 fffff000 2 b
ppcemb_tlb_check: TLB 20 address fffffe04 PID 3 <=> bfe4f000 fffff000 2 9
ppcemb_tlb_check: TLB 22 address fffffe04 PID 3 <=> b7c32000 fffff000 2 b
ppcemb_tlb_check: TLB 23 address fffffe04 PID 3 <=> b7bff000 fffff000 2 d
ppcemb_tlb_check: TLB 24 address fffffe04 PID 3 <=> 00913000 fffff000 2 d
ppcemb_tlb_check: TLB 25 address fffffe04 PID 3 <=> b7c64000 fffff000 3 b
ppcemb_tlb_check: TLB 26 address fffffe04 PID 3 <=> b7c2f000 fffff000 3 9
ppcemb_tlb_check: TLB 27 address fffffe04 PID 3 <=> b7bf5000 fffff000 3 d
ppcemb_tlb_check: TLB 28 address fffffe04 PID 3 <=> bfe4f000 fffff000 3 b
ppcemb_tlb_check: TLB 30 address fffffe04 PID 3 <=> 009bc000 fffff000 2 9
ppcemb_tlb_check: TLB 32 address fffffe04 PID 3 <=> 009c1000 fffff000 2 b
ppcemb_tlb_check: TLB 33 address fffffe04 PID 3 <=> 009c0000 fffff000 2 9
ppcemb_tlb_check: TLB 34 address fffffe04 PID 3 <=> 00970000 fffff000 2 d
ppcemb_tlb_check: TLB 35 address fffffe04 PID 3 <=> b7c44000 fffff000 3 b
ppcemb_tlb_check: TLB 36 address fffffe04 PID 3 <=> 00911000 fffff000 3 d
ppcemb_tlb_check: TLB 37 address fffffe04 PID 3 <=> 00912000 fffff000 3 d
ppcemb_tlb_check: TLB 38 address fffffe04 PID 3 <=> 0090e000 fffff000 3 d
ppcemb_tlb_check: TLB 39 address fffffe04 PID 3 <=> 00919000 fffff000 2 d
ppcemb_tlb_check: TLB 40 address fffffe04 PID 3 <=> 00971000 fffff000 2 d
ppcemb_tlb_check: TLB 41 address fffffe04 PID 3 <=> 009bf000 fffff000 2 9
ppcemb_tlb_check: TLB 42 address fffffe04 PID 3 <=> b7ba8000 fffff000 2 d
ppcemb_tlb_check: TLB 43 address fffffe04 PID 3 <=> 009c0000 fffff000 3 b
ppcemb_tlb_check: TLB 44 address fffffe04 PID 3 <=> 0090f000 fffff000 3 d
ppcemb_tlb_check: TLB 45 address fffffe04 PID 3 <=> 00910000 fffff000 3 d
ppcemb_tlb_check: TLB 46 address fffffe04 PID 3 <=> 008d9000 fffff000 3 d
ppcemb_tlb_check: TLB 47 address fffffe04 PID 3 <=> 00976000 fffff000 3 d
ppcemb_tlb_check: TLB 48 address fffffe04 PID 3 <=> b7bf4000 fffff000 3 d
ppcemb_tlb_check: TLB 49 address fffffe04 PID 3 <=> b7bd5000 fffff000 3 d
ppcemb_tlb_check: TLB 50 address fffffe04 PID 3 <=> b7c00000 fffff000 3 d
ppcemb_tlb_check: TLB 51 address fffffe04 PID 3 <=> b7ba7000 fffff000 3 d
ppcemb_tlb_check: TLB 52 address fffffe04 PID 3 <=> 0090d000 fffff000 3 d
ppcemb_tlb_check: TLB 53 address fffffe04 PID 3 <=> 00918000 fffff000 3 d
ppcemb_tlb_check: TLB 54 address fffffe04 PID 3 <=> 0097a000 fffff000 3 d
ppcemb_tlb_check: TLB 55 address fffffe04 PID 3 <=> b7bd6000 fffff000 3 d
ppcemb_tlb_check: TLB 56 address fffffe04 PID 3 <=> b7bf8000 fffff000 3 d
ppcemb_tlb_check: TLB 58 address fffffe04 PID 3 <=> b7c46000 fffff000 3 b
mmu40x_get_physical_address: access refused fffffe04 => ffffffffffffffff 4096 -1
NIP b7bd6744   LR b7bd66cc CTR b7bf471c XER 00000000 CPU#0
MSR 0000c030 HID0 00000300  HF 00004012 iidx 0 didx 0
TB 00000000 984786301 DECR 4294956920
GPR00 00000000b7bd66cc 00000000bfe4f9a0 00000000b7c6b470 0000000000000000
GPR04 00000000000000c8 00000000b7c30124 00000000009c140c 00000000fffffdfc
GPR08 000000002d740000 00000000009c12d0 0000000000000049 00000000bfe4f9a0
GPR12 0000000020004002 00000000009bfa94 0000000000000000 0000000000000000
GPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR24 0000000000000004 00000000bfe4f9f8 00000000009c0054 0000000000000000
GPR28 00000000bfe4f9a8 00000000b7c4642c 00000000b7c2fd58 00000000009c1210
CR 20004002  [ E  -  -  -  G  -  -  E  ]             RES ffffffff
  SRR0 b7bd672c  SRR1 0000c030    PVR 51210950 VRSAVE 00000000
SPRG0 00000049 SPRG1 bfe4f9a0  SPRG2 bfe4f9a0  SPRG3 00c3ee70
SPRG4 20004002 SPRG5 00000049  SPRG6 00000049  SPRG7 bfe4f9a0
   TCR 04000000   TSR c8000000    ESR 00800000   DEAR b7c4642c
  EVPR 00000000  SRR2 00000000   SRR3 00000000  PID 00000003
Raise exception at b7bd674c => DTLB (13) error=00
....

Re: [PATCH 02/15] ppc: Mark the 'taihu' machine as deprecated

[Philippe Mathieu-Daudé]

On 12/6/21 11:36, Cédric Le Goater wrote:
> From: Thomas Huth <thuth@redhat.com>
> 
> The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
> except for some external periphery. However, the periphery of the 'taihu'
> machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
> been implemented), so there is not much value added by this board. The users
> can use the 'ref405ep' machine to test their PPC405 code instead.
> 
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Message-Id: <20211203164904.290954-2-thuth@redhat.com>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  docs/about/deprecated.rst | 9 +++++++++
>  hw/ppc/ppc405_boards.c    | 1 +
>  2 files changed, 10 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>