Re: [Qemu-devel] [PATCH] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.

From: Paolo Bonzini <pbonzini@redhat.com>
To: He Chen <he.chen@linux.intel.com>, qemu-devel@nongnu.org
Cc: Richard Henderson <rth@twiddle.net>,
	Eduardo Habkost <ehabkost@redhat.com>,
	Luwei Kang <luwei.kang@intel.com>,
	Piotr Luc <Piotr.Luc@intel.com>
Subject: Re: [Qemu-devel] [PATCH] x86/cpuid:add AVX512_4VNNIW and AVX512_4FMAPS features.
Date: Fri, 28 Oct 2016 11:46:49 +0200	[thread overview]
Message-ID: <96512ad4-c051-2e0d-4947-6d75c4baa7cc@redhat.com> (raw)
In-Reply-To: <1477646144-7055-1-git-send-email-he.chen@linux.intel.com>

On 28/10/2016 11:15, He Chen wrote:
> From: Luwei Kang <luwei.kang@intel.com>
> 
> The spec can be found in Intel Software Developer Manual or in
> Instruction Set Extensions Programming Reference.
> 
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
> ---
>  target-i386/cpu.c | 19 ++++++++++++++++++-
>  target-i386/cpu.h |  4 ++++
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 1c57fce..68b4ffa 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -239,6 +239,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
>            CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
>            CPUID_7_0_EBX_RDSEED */
>  #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
> +#define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS)

This should be zero.  Otherwise looks good.

Paolo

>  #define TCG_APM_FEATURES 0
>  #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
>  #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
> @@ -444,6 +445,22 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>          .cpuid_reg = R_ECX,
>          .tcg_features = TCG_7_0_ECX_FEATURES,
>      },
> +    [FEAT_7_0_EDX] = {
> +        .feat_names = {
> +            NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +            NULL, NULL, NULL, NULL,
> +        },
> +        .cpuid_eax = 7,
> +        .cpuid_needs_ecx = true, .cpuid_ecx = 0,
> +        .cpuid_reg = R_EDX,
> +        .tcg_features = TCG_7_0_EDX_FEATURES,
> +    },
>      [FEAT_8000_0007_EDX] = {
>          .feat_names = {
>              NULL, NULL, NULL, NULL,
> @@ -2463,7 +2480,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>              if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
>                  *ecx |= CPUID_7_0_ECX_OSPKE;
>              }
> -            *edx = 0; /* Reserved */
> +            *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
>          } else {
>              *eax = 0;
>              *ebx = 0;
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index e645698..0e773f4 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -442,6 +442,7 @@ typedef enum FeatureWord {
>      FEAT_1_ECX,         /* CPUID[1].ECX */
>      FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
>      FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */
> +    FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */
>      FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
>      FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
>      FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
> @@ -628,6 +629,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>  #define CPUID_7_0_ECX_OSPKE    (1U << 4)
>  #define CPUID_7_0_ECX_RDPID    (1U << 22)
>  
> +#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
> +#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
> +
>  #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
>  #define CPUID_XSAVE_XSAVEC     (1U << 1)
>  #define CPUID_XSAVE_XGETBV1    (1U << 2)
> 