Re: [PATCH v4 6/8] drm/i915: reprogram NOA muxes on context switch when using perf

[Lionel Landwerlin <lionel.g.landwerlin@intel.com>]

On 09/05/18 18:48, Lionel Landwerlin wrote:
> @@ -1953,10 +1992,26 @@ static int gen8_emit_bb_start(struct i915_request *rq,
>   		rq->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
>   	}
>   
> -	cs = intel_ring_begin(rq, 6);
> +	cs = intel_ring_begin(rq, rq->engine->id == RCS ? 10 : 6);
>   	if (IS_ERR(cs))
>   		return PTR_ERR(cs);
>   
> +	if (rq->engine->id == RCS) {
> +		/*
> +		 * Leave some instructions to be written with an
> +		 * MI_BATCH_BUFFER_START to the i915/perf NOA reprogramming
> +		 * batchbuffer. We only turn those MI_NOOP into
> +		 * MI_BATCH_BUFFER_START when we detect a SSEU powergating
> +		 * configuration change that might affect NOA. This is only
> +		 * for the RCS.
> +		 */
> +		rq->perf_prog = intel_ring_offset(rq, cs);
> +		*cs++ = MI_NOOP;
> +		*cs++ = MI_NOOP;
> +		*cs++ = MI_NOOP;
> +		*cs++ = MI_NOOP; /* Aligning to 2 dwords */
> +	}
> +
I just realized that isn't going to work if a request is preempted, then 
later resubmitted after another context with a different powergating 
config...
This reprog bb won't be executed because the CS pointer should be past 
that point already.
It seems to make this approach unworkable?

Would a per-ctx-wa-bb call into the reprogramming buffer under 
MI_PREDICATE work?
LOAD rpcs into predicate_reg0
LOAD engine storage for last rpcs into prediate_reg1
PREDICATE reg0 == reg1
MI_LRI noa registers
PREDICATE unset
STORE rpcs into engine storage for last rpcs

Thanks,

-
Lionel
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