From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dhinakaran Pandiyan Subject: Re: [PATCH 4/5] drm/i915: Add PSR2 selective update status registers and bits definitions Date: Mon, 10 Dec 2018 23:51:26 -0800 Message-ID: <97444c13d54364c806f475c18d8317c65b06aeca.camel@intel.com> References: <20181204230032.6352-1-jose.souza@intel.com> <20181204230032.6352-4-jose.souza@intel.com> Reply-To: dhinakaran.pandiyan@intel.com Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8024B89EBD for ; Tue, 11 Dec 2018 07:51:30 +0000 (UTC) In-Reply-To: <20181204230032.6352-4-jose.souza@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: =?ISO-8859-1?Q?Jos=E9?= Roberto de Souza , intel-gfx@lists.freedesktop.org Cc: Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org T24gVHVlLCAyMDE4LTEyLTA0IGF0IDE1OjAwIC0wODAwLCBKb3PDqSBSb2JlcnRvIGRlIFNvdXph IHdyb3RlOgo+IFRoaXMgcmVnaXN0ZXIgY29udGFpbnMgaG93IG1hbnkgYmxvY2tzIHdhcyBzZW50 IGluIHRoZSBwYXN0IHNlbGVjdGl2ZQo+IHVwZGF0ZXMuCj4gVGhvc2UgcmVnaXN0ZXJzIGFyZSBu b3Qga2VwdCBzZXQgYWxsIHRoZSB0aW1lcyBidXQgcHVsbGluZyBpdCBhZnRlcgo+IGZsaXAKPiBj YW4gc2hvdyB0aGF0IHRoZSBleHBlY3RlZCB2YWx1ZXMgYXJlIHNldCBmb3IgdGhlIGN1cnJlbnQg ZnJhbWUgYW5kCj4gdGhlCj4gcHJldmlvdXMgb25lcyB0b28uCj4gCj4gQ2M6IFJvZHJpZ28gVml2 aSA8cm9kcmlnby52aXZpQGludGVsLmNvbT4KPiBDYzogRGhpbmFrYXJhbiBQYW5kaXlhbiA8ZGhp bmFrYXJhbi5wYW5kaXlhbkBpbnRlbC5jb20+Cj4gU2lnbmVkLW9mZi1ieTogSm9zw6kgUm9iZXJ0 byBkZSBTb3V6YSA8am9zZS5zb3V6YUBpbnRlbC5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2Ry bS9pOTE1L2k5MTVfcmVnLmggfCA2ICsrKysrKwo+ICAxIGZpbGUgY2hhbmdlZCwgNiBpbnNlcnRp b25zKCspCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgK PiBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgKPiBpbmRleCAwYTdkNjA1MDljYTcu LjdkNjM0ZjM0Y2E3ZCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3Jl Zy5oCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9yZWcuaAo+IEBAIC00MjQ4LDYg KzQyNDgsMTIgQEAgZW51bSB7Cj4gICNkZWZpbmUgRURQX1BTUjJfU1RBVFVTX1NUQVRFX01BU0sg ICAgICgweGYgPDwgMjgpCj4gICNkZWZpbmUgRURQX1BTUjJfU1RBVFVTX1NUQVRFX1NISUZUICAg IDI4Cj4gIAo+ICsjZGVmaW5lIEVEUF9QU1IyX1NVX1NUQVRVUwkJCQkJX01NSU8oMAo+IHg2Zjkx NCkKPiArI2RlZmluZSBFRFBfUFNSMl9TVV9TVEFUVVMyCQkJCQlfTU1JTygwCj4geDZGOTE4KQo+ ICsjZGVmaW5lIEVEUF9QU1IyX1NVX1NUQVRVUzMJCQkJCV9NTUlPKDAKPiB4NkY5MUMpCj4gKyNk ZWZpbmUgIEVEUF9QU1IyX1NVX1NUQVRVU19OVU1fU1VfQkxPQ0tTX0lOX0ZSQU1FX1NISUZUKGkp CSgoaSkgKgo+IDEwKQo+ICsjZGVmaW5lICBFRFBfUFNSMl9TVV9TVEFUVVNfTlVNX1NVX0JMT0NL U19JTl9GUkFNRV9NQVNLKGkpCSgweDNGRgo+IDw8ICgoaSkgKiAxMCkpCkhvdyBhYm91dCBtb3Zp bmcgdGhlIE1NSU8gc2VsZWN0aW9uIGxvZ2ljIHRvIHRoZSBtYWNyb3M/IAoKI2RlZmluZSBQU1Iy X1NVX0hJU1RPUlkgOAojZGVmaW5lIF9QU1IyX1NVX1NUQVRVU18wIDB4NmY5MTQKI2RlZmluZSBf UFNSMl9TVV9TVEFUVVNfMSAweDZmOTE4CiNkZWZpbmUgX1BTUjJfU1VfU1RBVFVTKGR3b3JkKSBf TU1JTyhfUElDS19FVkVOKChkd29yZCksXApfUFNSMl9TVV9TVEFUVVNfMCwgX1BTUjJfU1VfU1RB VFVTXzEpKQojZGVmaW5lIFBTUjJfU1VfU0hJRlQoZnJhbWUpICgoZnJhbWUpICUgMykgKiAxMAoj ZGVmaW5lIFBTUjJfU1VfTUFTSyhmcmFtZSkgICgweDNmZiA8PCBQU1IyX1NVX1NISUZUKGZyYW1l KSkKI2RlZmluZSBQU1IyX1NVX0JMT0NLUyhmcmFtZSkgX1BTUjJfU1VfU1RBVFVTKChmcmFtZSkg LyAzKQoKCj4gKwo+ICAvKiBWR0EgcG9ydCBjb250cm9sICovCj4gICNkZWZpbmUgQURQQQkJCV9N TUlPKDB4NjExMDApCj4gICNkZWZpbmUgUENIX0FEUEEgICAgICAgICAgICAgICAgX01NSU8oMHhl MTEwMCkKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCklu dGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRw czovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo=