From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40381C67871 for ; Sat, 6 Oct 2018 16:30:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 00FDE208E7 for ; Sat, 6 Oct 2018 16:30:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="BCcb4bdk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 00FDE208E7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727881AbeJFXeb (ORCPT ); Sat, 6 Oct 2018 19:34:31 -0400 Received: from bombadil.infradead.org ([198.137.202.133]:33812 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725266AbeJFXea (ORCPT ); Sat, 6 Oct 2018 19:34:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20170209; h=Content-Transfer-Encoding: Content-Type:In-Reply-To:MIME-Version:Date:Message-ID:From:References:Cc:To: Subject:Sender:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=eTBgH6DqMO6/18Ze4VhgcO9CjLgRjQl/mNnVbrWImLQ=; b=BCcb4bdkqHVSMxPYLivhsYq5h RHXLYkAE0yMlrExxt0h/rkWNfKtYGILGTkMzAcU+u7QS8D2/pucuCS9PEv6hJrumZuxa6XCwEFfpL dRHIk3jaTlqymVWJpdJeDeIcuJsfh3H/+VFxIO8ViBtB1G2Rf8NzsPp72heiSW2FzSZJc4NMUehLL XdwepnPHZFlYByqaS4+dcptIwIa/jbr/ekvHQ7mnxgZFiEdx3VsQqyxXX6FFjGBFzHhlXeASJUO2S FhEjIyvpZF7qP/Eu64KIXQAw9+Mtkg9V7cD8151//7KbU5DO4e0j90YcGm4Nby0la75v4q326c7Ao aL2jcAp0w==; Received: from static-50-53-52-16.bvtn.or.frontiernet.net ([50.53.52.16] helo=midway.dunlab) by bombadil.infradead.org with esmtpsa (Exim 4.90_1 #2 (Red Hat Linux)) id 1g8pTA-0005Xe-Jx; Sat, 06 Oct 2018 16:30:20 +0000 Subject: Re: [PATCH] Documentation/arm64: HugeTLB page implementation To: Punit Agrawal , linux-doc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, steve.capper@arm.com, Catalin Marinas , Will Deacon , Jonathan Corbet References: <20181005143458.17875-1-punit.agrawal@arm.com> From: Randy Dunlap Message-ID: <97e4e5fb-24ed-0545-414a-6a0c0116e6b8@infradead.org> Date: Sat, 6 Oct 2018 09:30:19 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20181005143458.17875-1-punit.agrawal@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Just some minor stuff (below). On 10/5/18 7:34 AM, Punit Agrawal wrote: > Arm v8 architecture supports multiple page sizes - 4k, 16k and > 64k. Based on the active page size, the Linux port supports > corresponding hugepage sizes at PMD and PUD(4k only) levels. > > In addition, the architecture also supports caching larger sized > ranges (composed of multiple entries) at the PTE and PMD level in the > TLBs using the contiguous bit. The Linux port makes use of this > architectural support to enable additional hugepage sizes. > > Describe the two different types of hugepages supported by the arm64 > kernel and the hugepage sizes enabled by each. > > Signed-off-by: Punit Agrawal > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Jonathan Corbet > --- > Documentation/arm64/hugetlbpage.txt | 39 +++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/arm64/hugetlbpage.txt > > diff --git a/Documentation/arm64/hugetlbpage.txt b/Documentation/arm64/hugetlbpage.txt > new file mode 100644 > index 000000000000..64ee24b88d27 > --- /dev/null > +++ b/Documentation/arm64/hugetlbpage.txt > @@ -0,0 +1,39 @@ > +HugeTLBpage on ARM64 > +==================== > + > +Hugepage relies on making efficient use of TLBs to improve performance of > +address translations. The benefit depends on both - > + > + - the size of hugepages > + - size of entries supported by the TLBs > + > +The ARM64 port supports two flavours of hugepages. > + > +1) Block mappings at the pud/pmd level > +-------------------------------------- > + > +These are regular hugepages where a pmd or a pud page table entry points to a > +block of memory. Regardless of the supported size of entries in TLB, block > +mappings reduces the depth of page table walk needed to translate hugepage reduce > +addresses. > + > +2) Using the Contiguous bit > +--------------------------- > + > +The architecture provides a contiguous bit in the translation table entries > +(D4.5.3, ARM DDI 0487C.a) that hints to the mmu to indicate that it is one of a preferably MMU > +contiguous set of entries that can be cached in a single TLB entry. > + > +The contiguous bit is used in Linux to increase the mapping size at the pmd and > +pte (last) level. The number of supported contiguous entries vary by page size varies > +and level of the page table. > + > + > + > +The following hugepage sizes are supported - > + > + CONT PTE PMD CONT PMD PUD > + -------- --- -------- --- > + 4K: 64K 2M 32M 1G > + 16K: 2M 32M 1G > + 64K: 2M 512M 16G > thanks, -- ~Randy From mboxrd@z Thu Jan 1 00:00:00 1970 From: rdunlap@infradead.org (Randy Dunlap) Date: Sat, 6 Oct 2018 09:30:19 -0700 Subject: [PATCH] Documentation/arm64: HugeTLB page implementation In-Reply-To: <20181005143458.17875-1-punit.agrawal@arm.com> References: <20181005143458.17875-1-punit.agrawal@arm.com> Message-ID: <97e4e5fb-24ed-0545-414a-6a0c0116e6b8@infradead.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Just some minor stuff (below). On 10/5/18 7:34 AM, Punit Agrawal wrote: > Arm v8 architecture supports multiple page sizes - 4k, 16k and > 64k. Based on the active page size, the Linux port supports > corresponding hugepage sizes at PMD and PUD(4k only) levels. > > In addition, the architecture also supports caching larger sized > ranges (composed of multiple entries) at the PTE and PMD level in the > TLBs using the contiguous bit. The Linux port makes use of this > architectural support to enable additional hugepage sizes. > > Describe the two different types of hugepages supported by the arm64 > kernel and the hugepage sizes enabled by each. > > Signed-off-by: Punit Agrawal > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Jonathan Corbet > --- > Documentation/arm64/hugetlbpage.txt | 39 +++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/arm64/hugetlbpage.txt > > diff --git a/Documentation/arm64/hugetlbpage.txt b/Documentation/arm64/hugetlbpage.txt > new file mode 100644 > index 000000000000..64ee24b88d27 > --- /dev/null > +++ b/Documentation/arm64/hugetlbpage.txt > @@ -0,0 +1,39 @@ > +HugeTLBpage on ARM64 > +==================== > + > +Hugepage relies on making efficient use of TLBs to improve performance of > +address translations. The benefit depends on both - > + > + - the size of hugepages > + - size of entries supported by the TLBs > + > +The ARM64 port supports two flavours of hugepages. > + > +1) Block mappings at the pud/pmd level > +-------------------------------------- > + > +These are regular hugepages where a pmd or a pud page table entry points to a > +block of memory. Regardless of the supported size of entries in TLB, block > +mappings reduces the depth of page table walk needed to translate hugepage reduce > +addresses. > + > +2) Using the Contiguous bit > +--------------------------- > + > +The architecture provides a contiguous bit in the translation table entries > +(D4.5.3, ARM DDI 0487C.a) that hints to the mmu to indicate that it is one of a preferably MMU > +contiguous set of entries that can be cached in a single TLB entry. > + > +The contiguous bit is used in Linux to increase the mapping size at the pmd and > +pte (last) level. The number of supported contiguous entries vary by page size varies > +and level of the page table. > + > + > + > +The following hugepage sizes are supported - > + > + CONT PTE PMD CONT PMD PUD > + -------- --- -------- --- > + 4K: 64K 2M 32M 1G > + 16K: 2M 32M 1G > + 64K: 2M 512M 16G > thanks, -- ~Randy