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From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC
Date: Fri, 01 Mar 2019 12:12:12 -0800	[thread overview]
Message-ID: <980955b200917222d858e8f43c416e328387a629.camel@intel.com> (raw)
In-Reply-To: <20190228013259.30026-5-jose.souza@intel.com>

On Wed, 2019-02-27 at 17:32 -0800, José Roberto de Souza wrote:
> When PSR2 is active aka after the number of frames programmed in
> PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
> interruptions causing IGT tests to fail due timeout.

Just to make sure we are documenting the issue correctly in the commit
message - is it the SU state when CRC generation stops or deep sleep?

-DK
> 
> Oddly that don't happen when PSR1 active, so here it switches from
> PSR2 to PSR1 while user is requesting pipe CRC.
> 
> Force setting mode_changed as true is necessary to atomic checks
> functions compute new PSR state, that is why it was added to
> intel_crtc_crc_prepare().
> 
> v3: Reusing intel_crtc_crc_prepare() and crc_enabled
> 
> v2: Changed commit description to describe that PSR2 inhibit CRC
> calculations.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pipe_crc.c | 1 +
>  drivers/gpu/drm/i915/intel_psr.c      | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
> b/drivers/gpu/drm/i915/intel_pipe_crc.c
> index f6d0b2aaffe2..e7ac24c33650 100644
> --- a/drivers/gpu/drm/i915/intel_pipe_crc.c
> +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
> @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private
> *dev_priv, struct drm_crtc *crtc,
>  		goto put_state;
>  	}
>  
> +	pipe_config->base.mode_changed = pipe_config->crc_enabled !=
> enable;
>  	pipe_config->crc_enabled = enable;
>  
>  	if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 6175b1d2e0c8..f7730b8b2ec0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	if (crtc_state->crc_enabled)
> +		return false;
> +
>  	return true;
>  }
>  

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  parent reply	other threads:[~2019-03-01 20:12 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-28  1:32 [PATCH v3 1/6] drm/i915/psr: Remove PSR2 FIXME José Roberto de Souza
2019-02-28  1:32 ` [PATCH v3 2/6] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset José Roberto de Souza
2019-02-28 16:39   ` Ville Syrjälä
2019-02-28 22:39     ` Souza, Jose
2019-02-28  1:32 ` [PATCH v3 3/6] drm/i915: Compute and commit color features in fastsets José Roberto de Souza
2019-02-28 16:41   ` Ville Syrjälä
2019-02-28  1:32 ` [PATCH v3 4/6] drm/i915/crc: Make IPS workaround generic José Roberto de Souza
2019-02-28 16:56   ` Ville Syrjälä
2019-02-28 17:04     ` Ville Syrjälä
2019-02-28 23:26     ` Souza, Jose
2019-03-01  1:06       ` Dhinakaran Pandiyan
2019-03-01  1:14         ` Souza, Jose
2019-03-01 20:07           ` Pandiyan, Dhinakaran
2019-03-01 13:35       ` Ville Syrjälä
2019-03-01 18:29         ` Souza, Jose
2019-02-28  1:32 ` [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC José Roberto de Souza
2019-02-28 16:58   ` Ville Syrjälä
2019-02-28 23:07     ` Souza, Jose
2019-03-01  1:57       ` Dhinakaran Pandiyan
2019-03-01  2:11         ` Souza, Jose
2019-03-01 20:12   ` Dhinakaran Pandiyan [this message]
2019-03-01 20:18     ` Souza, Jose
2019-03-01 20:45   ` Ville Syrjälä
2019-03-01 22:18     ` Souza, Jose
2019-02-28  1:32 ` [PATCH v3 6/6] drm/i915: Enable PSR2 by default José Roberto de Souza
2019-02-28  2:35 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/6] drm/i915/psr: Remove PSR2 FIXME Patchwork
2019-02-28  5:34 ` ✗ Fi.CI.IGT: failure " Patchwork

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