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(p200300ea8f08450058dae5ebc8671a2c.dip0.t-ipconnect.de. [2003:ea:8f08:4500:58da:e5eb:c867:1a2c]) by smtp.googlemail.com with ESMTPSA id g1sm19007wrb.27.2021.09.01.09.51.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Sep 2021 09:51:29 -0700 (PDT) To: =?UTF-8?Q?Pali_Roh=c3=a1r?= , =?UTF-8?Q?Jonas_Dre=c3=9fler?= Cc: Andy Shevchenko , Amitkumar Karwar , Ganapathi Bhat , Xinming Hu , Kalle Valo , "David S. Miller" , Jakub Kicinski , Tsuchiya Yuto , "open list:TI WILINK WIRELES..." , netdev , Linux Kernel Mailing List , linux-pci , Maximilian Luz , Andy Shevchenko , Bjorn Helgaas References: <20210830123704.221494-1-verdre@v0yd.nl> <20210830123704.221494-2-verdre@v0yd.nl> <7e38931e-2f1c-066e-088e-b27b56c1245c@v0yd.nl> <20210901155110.xgje2qrtq65loawh@pali> From: Heiner Kallweit Subject: Re: [PATCH 1/2] mwifiex: Use non-posted PCI register writes Message-ID: <985049b8-bad7-6f18-c94f-368059dd6f95@gmail.com> Date: Wed, 1 Sep 2021 18:51:21 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210901155110.xgje2qrtq65loawh@pali> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org On 01.09.2021 17:51, Pali Rohár wrote: > On Wednesday 01 September 2021 16:01:54 Jonas Dreßler wrote: >> On 8/30/21 2:49 PM, Andy Shevchenko wrote: >>> On Mon, Aug 30, 2021 at 3:38 PM Jonas Dreßler wrote: >>>> >>>> On the 88W8897 card it's very important the TX ring write pointer is >>>> updated correctly to its new value before setting the TX ready >>>> interrupt, otherwise the firmware appears to crash (probably because >>>> it's trying to DMA-read from the wrong place). >>>> This sounds somehow like the typical case where you write DMA descriptors and then ring the doorbell. This normally requires a dma_wmb(). Maybe something like that is missing here? Reading back all register writes may cause a certain performance impact, and if it can be avoided we should try to avoid it. >>>> Since PCI uses "posted writes" when writing to a register, it's not >>>> guaranteed that a write will happen immediately. That means the pointer >>>> might be outdated when setting the TX ready interrupt, leading to >>>> firmware crashes especially when ASPM L1 and L1 substates are enabled >>>> (because of the higher link latency, the write will probably take >>>> longer). >>>> >>>> So fix those firmware crashes by always forcing non-posted writes. We do >>>> that by simply reading back the register after writing it, just as a lot >>>> of other drivers do. >>>> >>>> There are two reproducers that are fixed with this patch: >>>> >>>> 1) During rx/tx traffic and with ASPM L1 substates enabled (the enabled >>>> substates are platform dependent), the firmware crashes and eventually a >>>> command timeout appears in the logs. That crash is fixed by using a >>>> non-posted write in mwifiex_pcie_send_data(). >>>> >>>> 2) When sending lots of commands to the card, waking it up from sleep in >>>> very quick intervals, the firmware eventually crashes. That crash >>>> appears to be fixed by some other non-posted write included here. >>> >>> Thanks for all this work! >>> >>> Nevertheless, do we have any commits that may be a good candidate to >>> be in the Fixes tag here? >>> >> >> I don't think there's any commit we could point to, given that the bug is >> probably somewhere in the firmware code. > > Then please add Cc: stable@vger.kernel.org tag into commit message. Such > bugfix is a good candidate for backporting into stable releases. > >>>> Signed-off-by: Jonas Dreßler