From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kay, Allen M" Subject: RE: [PATCH][VTD] enable integrated graphics passthrough for Calpella and Sandybridge Date: Thu, 10 Jun 2010 09:46:25 -0700 Message-ID: <987664A83D2D224EAE907B061CE93D530115129DF4@orsmsx505.amr.corp.intel.com> References: <987664A83D2D224EAE907B061CE93D530114C3D62D@orsmsx505.amr.corp.intel.com> <20100607074551.GB19463@valinux.co.jp> <987664A83D2D224EAE907B061CE93D5301150AC175@orsmsx505.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: Content-Language: en-US List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Stefano Stabellini Cc: "xen-devel@lists.xensource.com" , "Han, Weidong" , Guyader , Isaku Yamahata , Ian Pratt , Ross Philipson Jean List-Id: xen-devel@lists.xenproject.org > Can you register a dummy device at the address corresponding to IGD and > get the pci conf read and write calls directly from the functions you > pass to pci_register_device? I'm not sure what do you mean... The issue is IGD driver accesses some registers in device 0:0.0. However, = we don't want to passthrough platform's 0:0.0 to the guest as it will chang= e the guest's chipset wholesale thus create more problems than it solves. = For now, we are keeping the 440 chipset's 0:0.0 device but passthrough cert= ain register accesses. Isaku proposed register another set of read/write function for guest's devi= ce 0:0.0 instead of modifying existing functions. The advantage of this ap= proach is that original QEMU read/write function will be left unmodified fo= r IGD purpose. The disadvantage is this requires making a copy of exiting = code and redirect all read/write handling of 0:0.0 device to a function in = pt-graphics.c. I tried it out but found the resulting code a bit confusing= . Allen