diff for duplicates of <98C61C92-0D24-41C6-B9DA-8335B34D3B07@konsulko.com>
diff --git a/a/1.txt b/N1/1.txt
index 908642d..99d73ad 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,22 +1,41 @@
Hello Cristophe.
-> On Sep 10, 2018, at 7:34 AM, Christophe Leroy <christophe.leroy@c-s.fr> wrote:
->
-> On the powerpc8xx, handling 16k size pages requires to have page tables with 4 identical entries.
-
-Do you think a 16k page is useful? Back in the day, the goal was to keep the fault handling and management overhead as simple and generic as possible, as you know this affects the system performance. I understand there would be fewer page faults and more efficient use of the MMU resources with 16k, but if this comes at an overhead cost, is it really worth it?
-
-In addition to the normal 4k mapping, I had thought about using 512k mapping, which could be easily detected at level 2 (PMD), with a single entry loaded into the MMU. We would need an aux header or something from the executable/library to assist with knowing when this could be done. I never got around to it. :)
-
-The 8xx platforms tended to have smaller memory resources, so the 4k granularity was also useful in making better use of the available space.
+> On Sep 10, 2018, at 7:34 AM, Christophe Leroy =
+<christophe.leroy@c-s.fr> wrote:
+>=20
+> On the powerpc8xx, handling 16k size pages requires to have page =
+tables with 4 identical entries.
+
+Do you think a 16k page is useful? Back in the day, the goal was to =
+keep the fault handling and management overhead as simple and generic as =
+possible, as you know this affects the system performance. I understand =
+there would be fewer page faults and more efficient use of the MMU =
+resources with 16k, but if this comes at an overhead cost, is it really =
+worth it?
+
+In addition to the normal 4k mapping, I had thought about using 512k =
+mapping, which could be easily detected at level 2 (PMD), with a single =
+entry loaded into the MMU. We would need an aux header or something =
+from the executable/library to assist with knowing when this could be =
+done. I never got around to it. :)
+
+The 8xx platforms tended to have smaller memory resources, so the 4k =
+granularity was also useful in making better use of the available space.
> Would someone have an idea of an elegent way to handle that ?
-My suggestion would be to not change the PTE table, but have the fault handler detect a 16k page and load any one of the four entries based upon miss offset. Kinda use the same 4k miss hander, but with 16k knowledge. You wouldn’t save any PTE table space, but the MMU efficiency may be worth it. As I recall, the hardware may ignore/mask any LS bits, and there is PMD level information to utilize as well.
+My suggestion would be to not change the PTE table, but have the fault =
+handler detect a 16k page and load any one of the four entries based =
+upon miss offset. Kinda use the same 4k miss hander, but with 16k =
+knowledge. You wouldn=E2=80=99t save any PTE table space, but the MMU =
+efficiency may be worth it. As I recall, the hardware may ignore/mask =
+any LS bits, and there is PMD level information to utilize as well.
-It’s been a long time since I’ve investigated how things have evolved, glad it’s still in use, and I hope you at least have some fun with the development :)
+It=E2=80=99s been a long time since I=E2=80=99ve investigated how things =
+have evolved, glad it=E2=80=99s still in use, and I hope you at least =
+have some fun with the development :)
Thanks.
- — Dan
\ No newline at end of file
+ =E2=80=94 Dan
\ No newline at end of file
diff --git a/a/content_digest b/N1/content_digest
index ee67e6f..59e18c9 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -32,25 +32,44 @@
"\n",
"Hello Cristophe.\n",
"\n",
- "> On Sep 10, 2018, at 7:34 AM, Christophe Leroy <christophe.leroy\@c-s.fr> wrote:\n",
- "> \n",
- "> On the powerpc8xx, handling 16k size pages requires to have page tables with 4 identical entries.\n",
+ "> On Sep 10, 2018, at 7:34 AM, Christophe Leroy =\n",
+ "<christophe.leroy\@c-s.fr> wrote:\n",
+ ">=20\n",
+ "> On the powerpc8xx, handling 16k size pages requires to have page =\n",
+ "tables with 4 identical entries.\n",
"\n",
- "Do you think a 16k page is useful? Back in the day, the goal was to keep the fault handling and management overhead as simple and generic as possible, as you know this affects the system performance. I understand there would be fewer page faults and more efficient use of the MMU resources with 16k, but if this comes at an overhead cost, is it really worth it?\n",
+ "Do you think a 16k page is useful? Back in the day, the goal was to =\n",
+ "keep the fault handling and management overhead as simple and generic as =\n",
+ "possible, as you know this affects the system performance. I understand =\n",
+ "there would be fewer page faults and more efficient use of the MMU =\n",
+ "resources with 16k, but if this comes at an overhead cost, is it really =\n",
+ "worth it?\n",
"\n",
- "In addition to the normal 4k mapping, I had thought about using 512k mapping, which could be easily detected at level 2 (PMD), with a single entry loaded into the MMU. We would need an aux header or something from the executable/library to assist with knowing when this could be done. I never got around to it. :)\n",
+ "In addition to the normal 4k mapping, I had thought about using 512k =\n",
+ "mapping, which could be easily detected at level 2 (PMD), with a single =\n",
+ "entry loaded into the MMU. We would need an aux header or something =\n",
+ "from the executable/library to assist with knowing when this could be =\n",
+ "done. I never got around to it. :)\n",
"\n",
- "The 8xx platforms tended to have smaller memory resources, so the 4k granularity was also useful in making better use of the available space.\n",
+ "The 8xx platforms tended to have smaller memory resources, so the 4k =\n",
+ "granularity was also useful in making better use of the available space.\n",
"\n",
"> Would someone have an idea of an elegent way to handle that ?\n",
"\n",
- "My suggestion would be to not change the PTE table, but have the fault handler detect a 16k page and load any one of the four entries based upon miss offset. Kinda use the same 4k miss hander, but with 16k knowledge. You wouldn\342\200\231t save any PTE table space, but the MMU efficiency may be worth it. As I recall, the hardware may ignore/mask any LS bits, and there is PMD level information to utilize as well.\n",
+ "My suggestion would be to not change the PTE table, but have the fault =\n",
+ "handler detect a 16k page and load any one of the four entries based =\n",
+ "upon miss offset. Kinda use the same 4k miss hander, but with 16k =\n",
+ "knowledge. You wouldn=E2=80=99t save any PTE table space, but the MMU =\n",
+ "efficiency may be worth it. As I recall, the hardware may ignore/mask =\n",
+ "any LS bits, and there is PMD level information to utilize as well.\n",
"\n",
- "It\342\200\231s been a long time since I\342\200\231ve investigated how things have evolved, glad it\342\200\231s still in use, and I hope you at least have some fun with the development :)\n",
+ "It=E2=80=99s been a long time since I=E2=80=99ve investigated how things =\n",
+ "have evolved, glad it=E2=80=99s still in use, and I hope you at least =\n",
+ "have some fun with the development :)\n",
"\n",
"Thanks.\n",
"\n",
- "\t\342\200\224 Dan"
+ "\t=E2=80=94 Dan"
]
-b3a356c6c192491272886ab3a26f16c4184e82c66b7db84c75f79942ed89b85e
+88f97350bef4d9ee1cb78760be5367a42ab3e98b7d988131162452496952b5b1
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