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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Date: Sat, 9 Jul 2016 10:04:26 +0100
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Subject: Re: [Qemu-devel] [Qemu-ppc] [PULL 05/23] ppc: Enforce setting
 MSR:EE, IR and DR when MSR:PR is set
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To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, David Gibson <david@gibson.dropbear.id.au>, peter.maydell@linaro.org
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?UTF-8?Q?C=c3=a9dric_Le_Goater?= <clg@kaod.org>

On 09/07/16 04:08, Benjamin Herrenschmidt wrote:

> On Sat, 2016-07-09 at 13:00 +1000, Benjamin Herrenschmidt wrote:
>>> Additionally, hreg_compute_mem_idx() will treat PR=1 as DR=1/IR=1
>>> as well ! That means that if those old processors allow PR=1 and IR
>>> or DR=0 and MacOS uses it, we do have a TLB coherency problem in
>>> qemu.
>>
>> Wow, yes indeed, I see an MSR with PR=1 IR=0, IR=1 and EE=0 .. ugh.
> 
> Note that I see that happening with OS 9, but not with Darwin ... are
> you sure about OS X ?
> 
> Cheers,
> Ben.

Hmmm actually I think OS X might have been a red herring - I
double-checked and it looks like I was accidentally testing an illegal
combination, i.e. OS X 10.2 with -M mac99 which of course doesn't work.


ATB,

Mark.