From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Jan Kiszka <jan.kiszka@web.de>,
Luc Michel <luc.michel@greensocs.com>,
patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH for-3.0 2/2] hw/intc/arm_gic: Fix handling of GICD_ITARGETSR
Date: Thu, 12 Jul 2018 13:01:59 -0500 [thread overview]
Message-ID: <995c9d02-e2d3-0f91-d135-56b25a694819@linaro.org> (raw)
In-Reply-To: <20180712154152.32183-3-peter.maydell@linaro.org>
On 07/12/2018 10:41 AM, Peter Maydell wrote:
> The GICD_ITARGETSR implementation still has some 11MPCore behaviour
> that we were incorrectly using in our GICv1 and GICv2 implementations
> for the case where the interrupt number is less than GIC_INTERNAL.
> The desired behaviour here is:
> * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the
> CPU doing the read for irqs 29..31
> * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a
> number matching the CPU doing the read for all irqs < 32
>
> Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this
> is an 11MPCore GIC.
>
> Reported-by: Jan Kiszka <jan.kiszka@web.de>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/intc/arm_gic.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2018-07-12 18:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-12 15:41 [Qemu-devel] [PATCH for-3.0 0/2] a couple of GICv2 bug fixes Peter Maydell
2018-07-12 15:41 ` [Qemu-devel] [PATCH for-3.0 1/2] hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq() Peter Maydell
2018-07-12 17:57 ` Richard Henderson
2018-07-13 13:23 ` Luc Michel
2018-07-12 15:41 ` [Qemu-devel] [PATCH for-3.0 2/2] hw/intc/arm_gic: Fix handling of GICD_ITARGETSR Peter Maydell
2018-07-12 18:01 ` Richard Henderson [this message]
2018-07-13 13:24 ` Luc Michel
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