From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751927AbdBFXZc (ORCPT ); Mon, 6 Feb 2017 18:25:32 -0500 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:43673 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751456AbdBFXZ3 (ORCPT ); Mon, 6 Feb 2017 18:25:29 -0500 From: Chris Packham To: Stephen Boyd CC: "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" , Michael Turquette , Rob Herring , Mark Rutland , Jason Cooper , Andrew Lunn , "Gregory Clement" , Sebastian Hesselbarth , Russell King , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support Thread-Topic: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support Thread-Index: AQHSfc9C28CILxYjnUCUVa3hUDUJ8Q== Date: Mon, 6 Feb 2017 23:25:23 +0000 Message-ID: <9974653ab84040c3b12fad075790c123@svr-chch-ex1.atlnz.lc> References: <20170203034012.29399-1-chris.packham@alliedtelesis.co.nz> <20170203034012.29399-5-chris.packham@alliedtelesis.co.nz> <20170206231400.GM25384@codeaurora.org> Accept-Language: en-NZ, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [2001:df5:b000:22:7503:7357:8618:6207] Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v16NPacJ012513 On 07/02/17 12:14, Stephen Boyd wrote: > On 02/03, Chris Packham wrote: >> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support >> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. >> Port code from the Marvell supplied Linux kernel to support different >> PLL frequencies and provide clock gating support. >> >> Signed-off-by: Chris Packham >> --- >> .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 + >> .../bindings/clock/mvebu-gated-clock.txt | 11 ++ >> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 +- >> drivers/clk/mvebu/Makefile | 2 +- >> drivers/clk/mvebu/armada-xp.c | 13 -- >> drivers/clk/mvebu/mv98dx3236.c | 144 +++++++++++++++++++++ > > This mixes dts and clk driver changes. Any chance it can be split > up and just have the clk part go through clk tree? Otherwise, I > can ack this if you want to take it all through arm-soc? I'm happy to split it if it will make life easier. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Packham Subject: Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support Date: Mon, 6 Feb 2017 23:25:23 +0000 Message-ID: <9974653ab84040c3b12fad075790c123@svr-chch-ex1.atlnz.lc> References: <20170203034012.29399-1-chris.packham@alliedtelesis.co.nz> <20170203034012.29399-5-chris.packham@alliedtelesis.co.nz> <20170206231400.GM25384@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: Content-Language: en-US Sender: linux-clk-owner@vger.kernel.org To: Stephen Boyd Cc: "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" , Michael Turquette , Rob Herring , Mark Rutland , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Russell King , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" List-Id: devicetree@vger.kernel.org On 07/02/17 12:14, Stephen Boyd wrote:=0A= > On 02/03, Chris Packham wrote:=0A= >> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support= =0A= >> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.= =0A= >> Port code from the Marvell supplied Linux kernel to support different=0A= >> PLL frequencies and provide clock gating support.=0A= >>=0A= >> Signed-off-by: Chris Packham =0A= >> ---=0A= >> .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 +=0A= >> .../bindings/clock/mvebu-gated-clock.txt | 11 ++=0A= >> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 +-=0A= >> drivers/clk/mvebu/Makefile | 2 +-=0A= >> drivers/clk/mvebu/armada-xp.c | 13 --=0A= >> drivers/clk/mvebu/mv98dx3236.c | 144 ++++++++++++++= +++++++=0A= >=0A= > This mixes dts and clk driver changes. Any chance it can be split=0A= > up and just have the clk part go through clk tree? Otherwise, I=0A= > can ack this if you want to take it all through arm-soc?=0A= =0A= I'm happy to split it if it will make life easier.=0A= =0A= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Chris Packham To: Stephen Boyd CC: "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" , Michael Turquette , "Rob Herring" , Mark Rutland , "Jason Cooper" , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Russell King , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support Date: Mon, 6 Feb 2017 23:25:23 +0000 Message-ID: <9974653ab84040c3b12fad075790c123@svr-chch-ex1.atlnz.lc> References: <20170203034012.29399-1-chris.packham@alliedtelesis.co.nz> <20170203034012.29399-5-chris.packham@alliedtelesis.co.nz> <20170206231400.GM25384@codeaurora.org> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 List-ID: On 07/02/17 12:14, Stephen Boyd wrote:=0A= > On 02/03, Chris Packham wrote:=0A= >> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support= =0A= >> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.= =0A= >> Port code from the Marvell supplied Linux kernel to support different=0A= >> PLL frequencies and provide clock gating support.=0A= >>=0A= >> Signed-off-by: Chris Packham =0A= >> ---=0A= >> .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 +=0A= >> .../bindings/clock/mvebu-gated-clock.txt | 11 ++=0A= >> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 +-=0A= >> drivers/clk/mvebu/Makefile | 2 +-=0A= >> drivers/clk/mvebu/armada-xp.c | 13 --=0A= >> drivers/clk/mvebu/mv98dx3236.c | 144 ++++++++++++++= +++++++=0A= >=0A= > This mixes dts and clk driver changes. Any chance it can be split=0A= > up and just have the clk part go through clk tree? Otherwise, I=0A= > can ack this if you want to take it all through arm-soc?=0A= =0A= I'm happy to split it if it will make life easier.=0A= =0A= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris.Packham@alliedtelesis.co.nz (Chris Packham) Date: Mon, 6 Feb 2017 23:25:23 +0000 Subject: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support References: <20170203034012.29399-1-chris.packham@alliedtelesis.co.nz> <20170203034012.29399-5-chris.packham@alliedtelesis.co.nz> <20170206231400.GM25384@codeaurora.org> Message-ID: <9974653ab84040c3b12fad075790c123@svr-chch-ex1.atlnz.lc> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 07/02/17 12:14, Stephen Boyd wrote: > On 02/03, Chris Packham wrote: >> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support >> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. >> Port code from the Marvell supplied Linux kernel to support different >> PLL frequencies and provide clock gating support. >> >> Signed-off-by: Chris Packham >> --- >> .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 + >> .../bindings/clock/mvebu-gated-clock.txt | 11 ++ >> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 +- >> drivers/clk/mvebu/Makefile | 2 +- >> drivers/clk/mvebu/armada-xp.c | 13 -- >> drivers/clk/mvebu/mv98dx3236.c | 144 +++++++++++++++++++++ > > This mixes dts and clk driver changes. Any chance it can be split > up and just have the clk part go through clk tree? Otherwise, I > can ack this if you want to take it all through arm-soc? I'm happy to split it if it will make life easier.