Re: CP110 Comphy Issue

[Sven Auhagen <sven.auhagen@voleatech.de>]

Hi Miquèl,

Yes, I am sure the code uses ARM SMC and my ATF is very new, upstream version and supports it.
I am not using the marvell version.

I am also calling mvebu_comphy_power_off before initializing COMPHY and I can visually see my NICs resetting (LEDs off and back on) at Linux Kernel start.

The Kernel 5.4 RC8 boot hangs on PCIe Phy up.
I will send you logs tomorrow morning, when I have the device.

You can also see the marvell patches here:

https://voleatech-my.sharepoint.com/:u:/g/personal/sven_auhagen_voleatech_de/EcBFSVWdyWZNtI_4HjgEEN0B43WKQj_JwBYZgEbzFJaT_Q?e=h83gEy

Best
Sven

From: Miquel Raynal <miquel.raynal@bootlin.com>
Organisation: Bootlin
Date: Sunday, 24. November 2019 at 3:18 PM
To: Baruch Siach <baruch@tkos.co.il>
Cc: Sven Auhagen <sven.auhagen@voleatech.de>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>
Subject: Re: CP110 Comphy Issue

Hi Sven,

Baruch Siach <mailto:baruch@tkos.co.il> wrote on Sun, 24 Nov 2019 09:31:06
+0200:

Hi Sven, Miquel,
On Sun, Nov 24 2019, Sven Auhagen wrote:
> I am testing Kernel 5.4 RC8 with the new CP110 comphy initialization
> and it does not work for our custom board on CP 1 PCIE0.
>
> It hangs on phy up indefinitely during boot.
>
> CP0 PCIE0 works fine.
>
> I am using:
> +&cp1_pcie0 {
> +              pinctrl-names = "default";
> +              pinctrl-0 = <&cp0_pci1_reset_pins>;
> +              num-lanes = <1>;
> +              //num-viewport = <8>;
> +              reset-gpios = <&cp0_gpio2 1 GPIO_ACTIVE_LOW>;
> +              //rx-disable-gpio = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
> +              phys = <&cp1_comphy0 0>;
> +              phy-names = "cp1-pcie0-x1-phy";
> +              status = "okay";
> +};
>
> And this one works
>
> +&cp0_pcie0 {
> +              pinctrl-names = "default";
> +              pinctrl-0 = <&cp0_pci0_reset_pins>;
> +              num-lanes = <1>;
> +              //num-viewport = <8>;
> +              reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
> +              //rx-disable-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_LOW>;
> +              phys = <&cp0_comphy0 0>;
> +              phy-names = "cp0-pcie0-x1-phy";
> +              status = "okay";
> +};
> +
>
> I am using u-boot 2019.04 and ATF 2.1.
> PCIe is initialized by U-Boot.
>
> I was using a ported version of the comphy code from the marvell linux
> github before which did not have this problem.
>
> Let me know if I can debug anything here on my end.
One important bit of missing information is that the board is based on
Armada 8040.

Can you share the logs? How does it fail? Please share the full log.

Also, are you sure your ATF has COMPHY support? Recent kernels use ARM
SMC convention to request COMPHY initialization, which was probably not
the case before with the code ported from Marvell's BSP. Maybe if you
are using an official ATF release you don't have it (yet?).

Thanks,
Miquèl



Beste Grüße/Best regards

Sven Auhagen
Dipl. Math. oec., M.Sc.
Voleatech GmbH
HRB: B 754643
USTID: DE303643180
Grathwohlstr. 5
72762 Reutlingen
Tel: +49 7121539550
Fax: +49 7121539551
E-Mail: sven.auhagen@voleatech.de
www.voleatech.de<https://www.voleatech.de>
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