From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933114AbcE3Let (ORCPT ); Mon, 30 May 2016 07:34:49 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48100 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932192AbcE3Les (ORCPT ); Mon, 30 May 2016 07:34:48 -0400 Subject: Re: [PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80 To: Chen-Yu Tsai , Ulf Hansson , Maxime Ripard References: <1464505484-3661-1-git-send-email-wens@csie.org> <1464505484-3661-3-git-send-email-wens@csie.org> Cc: linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org From: Hans de Goede Message-ID: <99d78ff3-db4d-45cc-024a-d94583b56f35@redhat.com> Date: Mon, 30 May 2016 13:34:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: <1464505484-3661-3-git-send-email-wens@csie.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Mon, 30 May 2016 11:34:48 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 29-05-16 09:04, Chen-Yu Tsai wrote: > The MMC clock timings were incorrectly calculated, when the conversion > from delay value to delay phase was done. > > The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR > unusable. Unfortunately it seems different controllers on the same SoC > have different timings. The new settings are taken from mmc2, which is > commonly used with eMMC. Hmm, I'm not really all that familiar with mmc, but can't an external sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then we really need to update the driver to use the right per controller timings. > The settings for the slower timing modes seem to work despite being > wrong, so leave them be. If you're sure the timings are wrong, please fix them. Sometimes wrong timings do seem to work, but lead to unreliable communication, or turn out to work on some boards and not on others due to routing differences. Thanks & Regards, Hans > > Signed-off-by: Chen-Yu Tsai > --- > drivers/mmc/host/sunxi-mmc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c > index 7fc8b7aa83f0..5873dc344ab2 100644 > --- a/drivers/mmc/host/sunxi-mmc.c > +++ b/drivers/mmc/host/sunxi-mmc.c > @@ -970,8 +970,8 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { > [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, > [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, > [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, > - [SDXC_CLK_50M_DDR] = { .output = 90, .sample = 120 }, > - [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 120 }, > + [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, > + [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, > }; > > static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, > From mboxrd@z Thu Jan 1 00:00:00 1970 From: hdegoede@redhat.com (Hans de Goede) Date: Mon, 30 May 2016 13:34:42 +0200 Subject: [PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80 In-Reply-To: <1464505484-3661-3-git-send-email-wens@csie.org> References: <1464505484-3661-1-git-send-email-wens@csie.org> <1464505484-3661-3-git-send-email-wens@csie.org> Message-ID: <99d78ff3-db4d-45cc-024a-d94583b56f35@redhat.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On 29-05-16 09:04, Chen-Yu Tsai wrote: > The MMC clock timings were incorrectly calculated, when the conversion > from delay value to delay phase was done. > > The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR > unusable. Unfortunately it seems different controllers on the same SoC > have different timings. The new settings are taken from mmc2, which is > commonly used with eMMC. Hmm, I'm not really all that familiar with mmc, but can't an external sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then we really need to update the driver to use the right per controller timings. > The settings for the slower timing modes seem to work despite being > wrong, so leave them be. If you're sure the timings are wrong, please fix them. Sometimes wrong timings do seem to work, but lead to unreliable communication, or turn out to work on some boards and not on others due to routing differences. Thanks & Regards, Hans > > Signed-off-by: Chen-Yu Tsai > --- > drivers/mmc/host/sunxi-mmc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c > index 7fc8b7aa83f0..5873dc344ab2 100644 > --- a/drivers/mmc/host/sunxi-mmc.c > +++ b/drivers/mmc/host/sunxi-mmc.c > @@ -970,8 +970,8 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { > [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, > [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, > [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, > - [SDXC_CLK_50M_DDR] = { .output = 90, .sample = 120 }, > - [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 120 }, > + [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, > + [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, > }; > > static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, >