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[83.50.86.26]) by smtp.gmail.com with ESMTPSA id c8sm34750240wmq.34.2022.01.02.12.57.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 02 Jan 2022 12:57:15 -0800 (PST) Message-ID: <99e369be-ac50-5076-ee32-27576040806a@amsat.org> Date: Sun, 2 Jan 2022 21:57:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Subject: Re: [PATCH v2] hw/sd: Add SDHC support for SD card SPI-mode Content-Language: en-US To: frank.chang@sifive.com, qemu-devel@nongnu.org References: <20211228125719.14712-1-frank.chang@sifive.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20211228125719.14712-1-frank.chang@sifive.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-3.024, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, Bin Meng , Jim Shu , Alexander Bulekov , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/28/21 13:57, frank.chang@sifive.com wrote: > From: Frank Chang > > In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit > is not set to 1 correclty when the assigned SD image size is larger > than 2GB (SDHC). This will cause the SD card to be indentified as SDSC > incorrectly. CCS bit should be set to 1 if we are using SDHC. > > Also, as there's no power up emulation in SPI-mode. > The OCR register: Card power up status bit bit (busy) should also > be set to 1 when reset. (busy bit is set to LOW if the card has not > finished the power up routine.) > > Signed-off-by: Frank Chang > Reviewed-by: Jim Shu > Reviewed-by: Philippe Mathieu-Daudé > --- > hw/sd/sd.c | 24 +++++++++++++++++------- > 1 file changed, 17 insertions(+), 7 deletions(-) Thanks, queued to sdmmc-next.