From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32812) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bJYaH-0006Bq-6L for qemu-devel@nongnu.org; Sun, 03 Jul 2016 00:00:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bJYaD-0003wj-UN for qemu-devel@nongnu.org; Sun, 03 Jul 2016 00:00:41 -0400 Received: from [59.151.112.132] (port=34526 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bJYaD-0003uh-14 for qemu-devel@nongnu.org; Sun, 03 Jul 2016 00:00:37 -0400 References: <1464315131-25834-1-git-send-email-zhoujie2011@cn.fujitsu.com> <41b0c187-ade0-182e-46b5-afd3e99f1e36@cn.fujitsu.com> <20160620103226.0ff61b21@ul30vt.home> <20160620211306.66a6b249@t450s.home> <576935FC.1080503@easystack.cn> <20160621084443.330f932d@t450s.home> <20160621215626.71c99582@t450s.home> <113474d2-8408-db49-e7ef-8c6b736af866@cn.fujitsu.com> <468b752b-a161-902b-d4cc-489dfa18c21e@cn.fujitsu.com> <20160622094236.515549fa@t450s.home> <7746532f-2fad-1304-0df7-7cd25ba761af@cn.fujitsu.com> <20160627095418.659e6e5f@t450s.home> <20160627215808.1531a774@t450s.home> <7912dad0-0e37-603d-fdfe-bb4950b55f28@cn.fujitsu.com> <20160628084052.1e85a730@t450s.home> <689ac38f-96d7-9717-e9c4-d9926272cb86@cn.fujitsu.com> <20160629122242.2ac20254@t450s.home> From: Zhou Jie Message-ID: <99e88b46-8b8b-f7de-700f-8d644a7f005a@cn.fujitsu.com> Date: Sun, 3 Jul 2016 12:00:22 +0800 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v8 11/12] vfio: register aer resume notification handler for aer resume List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex Williamson Cc: izumi.taku@jp.fujitsu.com, caoj.fnst@cn.fujitsu.com, Chen Fan , qemu-devel@nongnu.org, mst@redhat.com Hi Alex, On 2016/6/30 9:45, Zhou Jie wrote: > Hi Alex, > > On 2016/6/30 2:22, Alex Williamson wrote: >> On Wed, 29 Jun 2016 16:54:05 +0800 >> Zhou Jie wrote: >> >>> Hi Alex, >>> >>>> And yet we have struct pci_dev.broken_intx_masking and we test for >>>> working DisINTx via pci_intx_mask_supported() rather than simply >>>> looking for a PCIe device. Some devices are broken and some simply >>>> don't follow the spec, so you're going to need to deal with that or >>>> exclude those devices. >>> For those devices I have no way to disable the INTx. >> >> disable_irq()? Clearly vfio-pci already manages these types of devices >> and can disable INTx. This is why I keep suggesting that maybe tearing >> the interrupt setup down completely is a more complete and reliable >> approach than masking in the command register. Unless we're going to >> exclude such devices from supporting this mode (which I don't condone), >> we must deal with them. > Thank you for tell me that. > Yes, I can use disable_irq to disable the pci device irq. > But should I enable the irq after reset? > I will dig into it. I will alter the VFIO driver like following. During err occurs and resume: 1. Make config space read only. 2. Disable INTx/MSI Interrupt. 3. Do nothing for bar regions. The following code will be modified. 1. vfio_pci_ioctl add a flag in vfio_device_info for workable_state support return workable_state in "struct vfio_pci_device" when user get info 2. vfio_pci_ioctl During err occurs and resume: if (cmd == VFIO_DEVICE_SET_IRQS || VFIO_DEVICE_RESET || VFIO_DEVICE_GET_PCI_HOT_RESET_INFO || VFIO_DEVICE_PCI_HOT_RESET) block for workable_state clearing 3. vfio_pci_write During err occurs and resume: ignore and return 0 4. vfio_pci_aer_err_detected Set workable_state to false in "struct vfio_pci_device" Disable INTx: If Disable INTx is support disable by PCI_COMMAND else disable by disable_irq function Disable MSI: disable by clearing the "Bus Master Enable" bit of PCI_COMMAND 5. vfio_pci_aer_resume Set workable_state to true in "struct vfio_pci_device" About INTx: According to the value of "vdev->ctx[0].masked" to decide whether to enable INTx About MSI: After reset the "Bus Master Enable" bit is default to 0. So user should process this after reset. Sincerely Zhou Jie