From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Wu, Jingjing" Subject: Re: [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library Date: Thu, 10 May 2018 22:39:44 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F81108F8E3@SHSMSX103.ccr.corp.intel.com> References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1525851801-16101-1-git-send-email-rosen.xu@intel.com> <1525851801-16101-2-git-send-email-rosen.xu@intel.com> <9BB6961774997848B5B42BEC655768F81108EC6C@SHSMSX103.ccr.corp.intel.com> <0E78D399C70DA940A335608C6ED296D739FD11D5@SHSMSX104.ccr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "Zhang, Roy Fan" , "Doherty, Declan" , "Richardson, Bruce" , "shreyansh.jain@nxp.com" , "Yigit, Ferruh" , "Ananyev, Konstantin" , "Zhang, Tianfei" , "Liu, Song" , "Wu, Hao" , "gaetan.rivet@6wind.com" To: "Xu, Rosen" , "dev@dpdk.org" , "thomas@monjalon.net" Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id EEF301BB50 for ; Fri, 11 May 2018 00:39:49 +0200 (CEST) In-Reply-To: <0E78D399C70DA940A335608C6ED296D739FD11D5@SHSMSX104.ccr.corp.intel.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Xu, Rosen > Sent: Thursday, May 10, 2018 8:21 PM > To: Wu, Jingjing ; dev@dpdk.org; thomas@monjalon.n= et > Cc: Zhang, Roy Fan ; Doherty, Declan > ; Richardson, Bruce ; > shreyansh.jain@nxp.com; Yigit, Ferruh ; Ananyev, = Konstantin > ; Zhang, Tianfei ;= Liu, Song > ; Wu, Hao ; gaetan.rivet@6wind.com > Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Lib= rary >=20 > Hi Jingjing, >=20 > > -----Original Message----- > > From: Wu, Jingjing > > Sent: Thursday, May 10, 2018 16:44 > > To: Xu, Rosen ; dev@dpdk.org; thomas@monjalon.net > > Cc: Xu, Rosen ; Zhang, Roy Fan > > ; Doherty, Declan ; > > Richardson, Bruce ; shreyansh.jain@nxp.com; > > Yigit, Ferruh ; Ananyev, Konstantin > > ; Zhang, Tianfei ; > > Liu, Song ; Wu, Hao ; > > gaetan.rivet@6wind.com > > Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS > > Library > > > > Hi, Rosen > > > > Few comments below. >=20 > Thanks a lot Jingjing. >=20 > > > > Thanks > > Jingjing > > > > [......] > > > +static struct rte_ifpga_device * > > > +ifpga_find_ifpga_dev(const struct rte_rawdev *rdev) { > > > + struct rte_ifpga_device *ifpga_dev =3D NULL; > > > + > > > + TAILQ_FOREACH(ifpga_dev, &ifpga_device_list, next) { > > > + if (rdev && > > rdev -> ifpage_dev ?? >=20 > Rdev doesn't has this variable. I mean "if (ifpag_dev" & to replace "rdev" >=20 > > > + ifpga_dev->rdev && > > > + ifpga_dev->rdev =3D=3D rdev) > > > + return ifpga_dev; > > > + } > > > + return NULL; > > > +} > > > + > > > +static struct rte_afu_device * > > > +ifpga_find_afu_dev(const struct rte_ifpga_device *ifpga_dev, > > > + const struct rte_afu_id *afu_id) > > > +{ > > > + struct rte_afu_device *afu_dev =3D NULL; > > > + > > > + TAILQ_FOREACH(afu_dev, &ifpga_dev->afu_list, next) { > > > + if (!ifpga_afu_id_cmp(&afu_dev->id, afu_id)) > > Add checking afu_dev? >=20 > Fixed. >=20 > > [...] > > > > > +static int > > > +ifpga_parse(const char *name, void *addr) { > > > + int *out =3D addr; > > > + struct rte_rawdev *rawdev =3D NULL; > > > + char rawdev_name[RTE_RAWDEV_NAME_MAX_LEN]; > > > + char *c1 =3D NULL, *c2 =3D NULL; > > According to coding style, we need to two lines for the definition like= : > > char *c1 =3D NULL; > > char *c2 =3D NULL; >=20 > Fixed >=20 > > > + int port =3D IFPGA_BUS_DEV_PORT_MAX; > > > + char str_port[8]; > > > + int str_port_len =3D 0; > > > + int ret; > > > + > > > + memset(str_port, 0, 8); > > > + c1 =3D strchr(name, '|'); > > > + if (c1 !=3D NULL) { > > > + str_port_len =3D c1-name; > > According to coding style, spaces are required around opreations. >=20 > Fixed. >=20 > > > + c2 =3D c1+1; > > > + }