From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3274BC31E5B for ; Tue, 18 Jun 2019 16:07:58 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id C187D20B1F for ; Tue, 18 Jun 2019 16:07:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C187D20B1F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A83141C213; Tue, 18 Jun 2019 18:07:47 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 5103F1C200 for ; Tue, 18 Jun 2019 18:07:40 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Jun 2019 09:07:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,389,1557212400"; d="scan'208";a="334899770" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga005.jf.intel.com with ESMTP; 18 Jun 2019 09:07:37 -0700 Received: from fmsmsx152.amr.corp.intel.com (10.18.125.5) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 18 Jun 2019 09:07:37 -0700 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by FMSMSX152.amr.corp.intel.com (10.18.125.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 18 Jun 2019 09:07:36 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.83]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.89]) with mapi id 14.03.0439.000; Wed, 19 Jun 2019 00:07:34 +0800 From: "Wu, Jingjing" To: "Li, Xiaoyun" , "Wiles, Keith" , "Liang, Cunming" , "Maslekar, Omkar" CC: "dev@dpdk.org" Thread-Topic: [PATCH v6 2/6] raw/ntb: add intel ntb support Thread-Index: AQHVJXszSeBV1yP1kkK5CmwS7ccMTKahhXMA Date: Tue, 18 Jun 2019 16:07:34 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F81145FE76@SHSMSX103.ccr.corp.intel.com> References: <20190614021940.78631-1-xiaoyun.li@intel.com> <20190618021055.12709-1-xiaoyun.li@intel.com> <20190618021055.12709-3-xiaoyun.li@intel.com> In-Reply-To: <20190618021055.12709-3-xiaoyun.li@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTdiMzg4YjMtYWIxYy00MWQ0LWJiOWQtYzQyMmVlMzk3ODc5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMG5SdFo2cTZMQXl0dzJyMFRuVEROaHg1RkRmMEV3bGR6QTFJUVJCRVB6R3d5Vkd5WnhmSkx4blhHZ3l0dkZNbSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v6 2/6] raw/ntb: add intel ntb support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" One general comment: Think about to use rte_read32() and rte_write32() when reading and writing = registers. Or you can define a Macro or inline function for NTB driver to t= ouch registers. Then you can omit lots of "(char *)hw->pci_dev->mem_resourc= e[0].addr " and "*((volatile uint32_t *)" like things. It will make the cod= e much easier to read. > +static void * > +intel_ntb_get_peer_mw_addr(struct rte_rawdev *dev, int mw_idx) > +{ > + struct ntb_hw *hw =3D dev->dev_private; > + uint8_t bar; > + > + if (hw =3D=3D NULL) { > + NTB_LOG(ERR, "Invalid device."); > + return 0; > + } > + > + if (mw_idx < 0 || mw_idx > hw->mw_cnt) { mw_idx >=3D hw->mw_cnt? [...] > +static int > +intel_ntb_mw_set_trans(struct rte_rawdev *dev, int mw_idx, > + uint64_t addr, uint64_t size) > +{ > + struct ntb_hw *hw =3D dev->dev_private; > + void *xlat_addr, *limit_addr; > + uint64_t xlat_off, limit_off; > + uint64_t base, limit; > + uint8_t bar; > + > + if (hw =3D=3D NULL) { > + NTB_LOG(ERR, "Invalid device."); > + return -EINVAL; > + } > + > + if (mw_idx < 0 || mw_idx > hw->mw_cnt) { Same as above. [...] > +static uint32_t > +intel_ntb_spad_read(struct rte_rawdev *dev, int spad, bool peer) > +{ > + struct ntb_hw *hw =3D dev->dev_private; > + uint32_t spad_v, reg_off; > + void *reg_addr; > + > + if (spad < 0 || spad >=3D hw->spad_cnt) { > + NTB_LOG(ERR, "Invalid spad reg index."); > + return 0; > + } > + > + /* When peer is true, read peer spad reg */ > + if (peer) > + reg_off =3D XEON_B2B_SPAD_OFFSET; > + else > + reg_off =3D XEON_IM_SPAD_OFFSET; How about one line if check is simple? reg_off =3D peer ? XEON_B2B_SPAD_OFFSET : XEON_IM_SPAD_OFFSET; Thanks Jingjing