From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Wu, Jingjing" Subject: Re: [PATCH v2 24/33] i40e/base: get pf_id from HW rather than PCI function Date: Fri, 8 May 2015 03:20:00 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8C182EB@SHSMSX104.ccr.corp.intel.com> References: <1429518150-28098-1-git-send-email-helin.zhang@intel.com> <1430406219-23901-1-git-send-email-helin.zhang@intel.com> <1430406219-23901-25-git-send-email-helin.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "Kenguva, Monica" , "Murray, Steven J" , "Nelson, Shannon" To: "Zhang, Helin" , "dev-VfR2kkLFssw@public.gmane.org" Return-path: In-Reply-To: <1430406219-23901-25-git-send-email-helin.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org> Content-Language: en-US List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces-VfR2kkLFssw@public.gmane.org Sender: "dev" Acked-by: Jingjing Wu > -----Original Message----- > From: Zhang, Helin > Sent: Thursday, April 30, 2015 11:04 PM > To: dev-VfR2kkLFssw@public.gmane.org > Cc: Cao, Min; Xu, Qian Q; Wu, Jingjing; Liu, Jijiang; Kenguva, Monica; Pa= tel, > Rashmin N; Murray, Steven J; Nelson, Shannon; Zhang, Helin > Subject: [PATCH v2 24/33] i40e/base: get pf_id from HW rather than PCI > function >=20 > Getting the pf_id from the function number was a good place to start, but > when the PF was setup in pass-thru mode, the PCI bus/device/function was > virtualized and the number in the VM is different from the number in the > bare metal. This caused HW configuration issues when the wrong pf_id was > used to set up the HMC and other structures. The PF_FUNC_RID register has > the real bus/device/function information as configured by the BIOS, so us= e > that for a better number. >=20 > Signed-off-by: Helin Zhang > --- > lib/librte_pmd_i40e/i40e/i40e_common.c | 23 +++++++++++------------ > 1 file changed, 11 insertions(+), 12 deletions(-) >=20 > diff --git a/lib/librte_pmd_i40e/i40e/i40e_common.c > b/lib/librte_pmd_i40e/i40e/i40e_common.c > index 705b9dd..03980b9 100644 > --- a/lib/librte_pmd_i40e/i40e/i40e_common.c > +++ b/lib/librte_pmd_i40e/i40e/i40e_common.c > @@ -592,7 +592,7 @@ enum i40e_status_code i40e_validate_mac_addr(u8 > *mac_addr) enum i40e_status_code i40e_init_shared_code(struct i40e_hw > *hw) { > enum i40e_status_code status =3D I40E_SUCCESS; > - u32 reg; > + u32 port, ari, func_rid; >=20 > DEBUGFUNC("i40e_init_shared_code"); >=20 > @@ -607,18 +607,17 @@ enum i40e_status_code > i40e_init_shared_code(struct i40e_hw *hw) >=20 > hw->phy.get_link_info =3D true; >=20 > - /* Determine port number */ > - reg =3D rd32(hw, I40E_PFGEN_PORTNUM); > - reg =3D ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >> > - I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT); > - hw->port =3D (u8)reg; > - > - /* Determine the PF number based on the PCI fn */ > - reg =3D rd32(hw, I40E_GLPCI_CAPSUP); > - if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK) > - hw->pf_id =3D (u8)((hw->bus.device << 3) | hw->bus.func); > + /* Determine port number and PF number*/ > + port =3D (rd32(hw, I40E_PFGEN_PORTNUM) & > I40E_PFGEN_PORTNUM_PORT_NUM_MASK) > + >> > I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; > + hw->port =3D (u8)port; > + ari =3D (rd32(hw, I40E_GLPCI_CAPSUP) & > I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> > + > I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; > + func_rid =3D rd32(hw, I40E_PF_FUNC_RID); > + if (ari) > + hw->pf_id =3D (u8)(func_rid & 0xff); > else > - hw->pf_id =3D (u8)hw->bus.func; > + hw->pf_id =3D (u8)(func_rid & 0x7); >=20 > status =3D i40e_init_nvm(hw); > return status; > -- > 1.8.1.4