From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF459C433ED for ; Mon, 17 May 2021 14:35:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A21561C98 for ; Mon, 17 May 2021 14:35:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240056AbhEQOgv convert rfc822-to-8bit (ORCPT ); Mon, 17 May 2021 10:36:51 -0400 Received: from aposti.net ([89.234.176.197]:33348 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239207AbhEQOcR (ORCPT ); Mon, 17 May 2021 10:32:17 -0400 Date: Mon, 17 May 2021 15:30:45 +0100 From: Paul Cercueil Subject: Re: [PATCH] drm/ingenic: Fix pixclock rate for 24-bit serial panels To: Daniel Vetter Cc: David Airlie , Sam Ravnborg , od@zcrc.me, linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Message-Id: <9N99TQ.6E5XN4XTCLTT1@crapouillou.net> In-Reply-To: References: <20210323144008.166248-1-paul@crapouillou.net> <6DP1TQ.W6B9JRRW1OY5@crapouillou.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Daniel, Le lun., mai 17 2021 at 15:15:59 +0200, Daniel Vetter a écrit : > On Thu, May 13, 2021 at 01:29:30PM +0100, Paul Cercueil wrote: >> Hi, >> >> Almost two months later, > > Since you're committer it's expected that you go actively out to look > for > review or trade with someone else who has some patches that need a > quick > look. It will not happen automatically, this is on you. I maintain all drivers, platform code and DTS for Ingenic SoCs so I do my part, just not in this subsystem. > Also generally after 2 weeks the patch is lost and you need to ping > it. OK. Then I guess I'll just include this one in a future patchset. > -Daniel Cheers, -Paul >> >> >> Le mar., mars 23 2021 at 14:40:08 +0000, Paul Cercueil >> a écrit : >> > When using a 24-bit panel on a 8-bit serial bus, the pixel clock >> > requested by the panel has to be multiplied by 3, since the >> subpixels >> > are shifted sequentially. >> > >> > The code (in ingenic_drm_encoder_atomic_check) already computed >> > crtc_state->adjusted_mode->crtc_clock accordingly, but >> clk_set_rate() >> > used crtc_state->adjusted_mode->clock instead. >> > >> > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when >> using a >> > 3x8-bit panel") >> > Cc: stable@vger.kernel.org # v5.10 >> > Signed-off-by: Paul Cercueil >> >> Can I get an ACK for my patch? >> >> Thanks! >> -Paul >> >> > --- >> > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > index d60e1eefc9d1..cba68bf52ec5 100644 >> > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > @@ -342,7 +342,7 @@ static void >> ingenic_drm_crtc_atomic_flush(struct >> > drm_crtc *crtc, >> > if (priv->update_clk_rate) { >> > mutex_lock(&priv->clk_mutex); >> > clk_set_rate(priv->pix_clk, >> > - crtc_state->adjusted_mode.clock * 1000); >> > + crtc_state->adjusted_mode.crtc_clock * 1000); >> > priv->update_clk_rate = false; >> > mutex_unlock(&priv->clk_mutex); >> > } >> > -- >> > 2.30.2 >> > >> >> > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA8C7C43462 for ; Mon, 17 May 2021 14:31:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 971F761876 for ; Mon, 17 May 2021 14:31:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 971F761876 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=crapouillou.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E0FB26E98F; Mon, 17 May 2021 14:31:00 +0000 (UTC) Received: from aposti.net (aposti.net [89.234.176.197]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B11D6E98F for ; Mon, 17 May 2021 14:30:59 +0000 (UTC) Date: Mon, 17 May 2021 15:30:45 +0100 From: Paul Cercueil Subject: Re: [PATCH] drm/ingenic: Fix pixclock rate for 24-bit serial panels To: Daniel Vetter Message-Id: <9N99TQ.6E5XN4XTCLTT1@crapouillou.net> In-Reply-To: References: <20210323144008.166248-1-paul@crapouillou.net> <6DP1TQ.W6B9JRRW1OY5@crapouillou.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-mips@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, od@zcrc.me, stable@vger.kernel.org, Sam Ravnborg Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Daniel, Le lun., mai 17 2021 at 15:15:59 +0200, Daniel Vetter =20 a =E9crit : > On Thu, May 13, 2021 at 01:29:30PM +0100, Paul Cercueil wrote: >> Hi, >>=20 >> Almost two months later, >=20 > Since you're committer it's expected that you go actively out to look=20 > for > review or trade with someone else who has some patches that need a=20 > quick > look. It will not happen automatically, this is on you. I maintain all drivers, platform code and DTS for Ingenic SoCs so I do=20 my part, just not in this subsystem. > Also generally after 2 weeks the patch is lost and you need to ping=20 > it. OK. Then I guess I'll just include this one in a future patchset. > -Daniel Cheers, -Paul >>=20 >>=20 >> Le mar., mars 23 2021 at 14:40:08 +0000, Paul Cercueil >> a =E9crit : >> > When using a 24-bit panel on a 8-bit serial bus, the pixel clock >> > requested by the panel has to be multiplied by 3, since the=20 >> subpixels >> > are shifted sequentially. >> > >> > The code (in ingenic_drm_encoder_atomic_check) already computed >> > crtc_state->adjusted_mode->crtc_clock accordingly, but=20 >> clk_set_rate() >> > used crtc_state->adjusted_mode->clock instead. >> > >> > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when=20 >> using a >> > 3x8-bit panel") >> > Cc: stable@vger.kernel.org # v5.10 >> > Signed-off-by: Paul Cercueil >>=20 >> Can I get an ACK for my patch? >>=20 >> Thanks! >> -Paul >>=20 >> > --- >> > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > index d60e1eefc9d1..cba68bf52ec5 100644 >> > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > @@ -342,7 +342,7 @@ static void=20 >> ingenic_drm_crtc_atomic_flush(struct >> > drm_crtc *crtc, >> > if (priv->update_clk_rate) { >> > mutex_lock(&priv->clk_mutex); >> > clk_set_rate(priv->pix_clk, >> > - crtc_state->adjusted_mode.clock * 1000); >> > + crtc_state->adjusted_mode.crtc_clock * 1000); >> > priv->update_clk_rate =3D false; >> > mutex_unlock(&priv->clk_mutex); >> > } >> > -- >> > 2.30.2 >> > >>=20 >>=20 >=20 > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch