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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id o12sm4459553wrx.82.2021.01.27.14.10.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 14:10:10 -0800 (PST) Subject: Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device To: Peter Maydell References: <20210121190622.22000-1-peter.maydell@linaro.org> <20210121190622.22000-17-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <9a64e598-91e8-7547-3b5c-ad2a8c8496e3@amsat.org> Date: Wed, 27 Jan 2021 23:10:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , qemu-arm , Luc Michel , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/25/21 12:48 PM, Peter Maydell wrote: > On Thu, 21 Jan 2021 at 22:13, Philippe Mathieu-Daudé wrote: >> On 1/21/21 8:06 PM, Peter Maydell wrote: >>> Convert the SSYS code in the Stellaris boards (which encapsulates the >>> system registers) to a proper QOM device. This will provide us with >>> somewhere to put the output Clock whose frequency depends on the >>> setting of the PLL configuration registers. >>> >>> This is a migration compatibility break for lm3s811evb, lm3s6965evb. >>> >>> We use 3-phase reset here because the Clock will need to propagate >>> its value in the hold phase. >>> >>> For the moment we reset the device during the board creation so that >>> the system_clock_scale global gets set; this will be removed in a >>> subsequent commit. > >>> + >>> +struct ssys_state { >>> + SysBusDevice parent_obj; >>> + >>> MemoryRegion iomem; >>> uint32_t pborctl; >>> uint32_t ldopctl; >>> @@ -371,11 +376,18 @@ typedef struct { >>> uint32_t dcgc[3]; >>> uint32_t clkvclr; >>> uint32_t ldoarst; >>> + qemu_irq irq; >>> + /* Properties (all read-only registers) */ >>> uint32_t user0; >>> uint32_t user1; >>> - qemu_irq irq; >>> - stellaris_board_info *board; >>> -} ssys_state; >>> + uint32_t did0; >>> + uint32_t did1; >>> + uint32_t dc0; >>> + uint32_t dc1; >>> + uint32_t dc2; >>> + uint32_t dc3; >>> + uint32_t dc4; >> >> Shouldn't these be class properties? > > Could you elaborate on what you think the code ought to look like? I am thinking something similar how Igor asked me to implement RaspiMachineClass::board_rev in hw/arm/raspi.c, as the did/dc registers are read-only. Anyhow this is 1/ probably not necessary and 2/ out of the scope of this series, this patch is already complex enough, and the work is done. > I just used the usual thing of defining uint32 qdev properties so we > can set these values when we create the device, as a replacement > for the existing code which either reaches directly into the > state struct to set the user0/user1 values or sets the > stellaris_board_info pointer in the state struct. No problem. Reviewed-by: Philippe Mathieu-Daudé