Re: [RESEND PATCH] dmaengine: tegra210-adma: Don't program FIFO threshold

[Sameer Pujar <spujar@nvidia.com>]

On 7/5/2019 2:45 PM, Jon Hunter wrote:
> From: Jonathan Hunter <jonathanh@nvidia.com>
>
> The Tegra210 ADMA supports two modes for transferring data to a FIFO
> which are ...
>
> 1. Transfer data to/from the FIFO as soon as a single burst can be
>     transferred.
> 2. Transfer data to/from the FIFO based upon FIFO thresholds, where
>     the FIFO threshold is specified in terms on multiple bursts.
>
> Currently, the ADMA driver programs the FIFO threshold values in the
> FIFO_CTRL register, but never enables the transfer mode that uses
> these threshold values. Given that these have never been used so far,
> simplify the ADMA driver by removing the programming of these threshold
> values.
>
> Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com>
> Acked-by: Thierry Reding <treding@nvidia.com>
> ---
>
> Resending the patch rebased on top next-20190704. I have added Thierry's
> ACK as well.
>
>   drivers/dma/tegra210-adma.c | 12 ++----------
>   1 file changed, 2 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
> index 2805853e963f..d8646a49ba5b 100644
> --- a/drivers/dma/tegra210-adma.c
> +++ b/drivers/dma/tegra210-adma.c
> @@ -42,12 +42,8 @@
>   #define ADMA_CH_CONFIG_MAX_BUFS				8
>   
>   #define ADMA_CH_FIFO_CTRL				0x2c
> -#define TEGRA210_ADMA_CH_FIFO_CTRL_OFLWTHRES(val)	(((val) & 0xf) << 24)
> -#define TEGRA210_ADMA_CH_FIFO_CTRL_STRVTHRES(val)	(((val) & 0xf) << 16)
>   #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val)		(((val) & 0xf) << 8)
>   #define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val)		((val) & 0xf)
> -#define TEGRA186_ADMA_CH_FIFO_CTRL_OFLWTHRES(val)	(((val) & 0x1f) << 24)
> -#define TEGRA186_ADMA_CH_FIFO_CTRL_STRVTHRES(val)	(((val) & 0x1f) << 16)
>   #define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val)		(((val) & 0x1f) << 8)
>   #define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val)		((val) & 0x1f)
>   
> @@ -64,14 +60,10 @@
>   
>   #define TEGRA_ADMA_BURST_COMPLETE_TIME			20
>   
> -#define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_OFLWTHRES(1) | \
> -				    TEGRA210_ADMA_CH_FIFO_CTRL_STRVTHRES(1) | \
> -				    TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3)    | \
> +#define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
>   				    TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3))
>   
> -#define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_OFLWTHRES(1) | \
> -				    TEGRA186_ADMA_CH_FIFO_CTRL_STRVTHRES(1) | \
> -				    TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3)    | \
> +#define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \
>   				    TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3))
>   
>   #define ADMA_CH_REG_FIELD_VAL(val, mask, shift)	(((val) & mask) << shift)
Acked-by: Sameer Pujar <spujar@nvidia.com>