From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DB52C433DF for ; Wed, 1 Jul 2020 08:04:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E0B4D2073E for ; Wed, 1 Jul 2020 08:04:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728520AbgGAIEM (ORCPT ); Wed, 1 Jul 2020 04:04:12 -0400 Received: from foss.arm.com ([217.140.110.172]:41924 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728258AbgGAIEJ (ORCPT ); Wed, 1 Jul 2020 04:04:09 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62B9B31B; Wed, 1 Jul 2020 01:04:07 -0700 (PDT) Received: from [10.57.4.20] (unknown [10.57.4.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B2AD43F68F; Wed, 1 Jul 2020 01:04:03 -0700 (PDT) Subject: Re: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo To: Bhupesh Sharma , linux-arm-kernel@lists.infradead.org, x86@kernel.org Cc: Mark Rutland , Kazuhito Hagio , Steve Capper , Catalin Marinas , Ard Biesheuvel , kexec@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse , Dave Anderson , bhupesh.linux@gmail.com, Will Deacon References: <1589395957-24628-1-git-send-email-bhsharma@redhat.com> <1589395957-24628-3-git-send-email-bhsharma@redhat.com> From: Amit Kachhap Message-ID: <9b44a21d-93e0-8e5d-019c-fd360bf0504b@arm.com> Date: Wed, 1 Jul 2020 13:34:00 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <1589395957-24628-3-git-send-email-bhsharma@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bhupesh, On 5/14/20 12:22 AM, Bhupesh Sharma wrote: > vabits_actual variable on arm64 indicates the actual VA space size, > and allows a single binary to support both 48-bit and 52-bit VA > spaces. > > If the ARMv8.2-LVA optional feature is present, and we are running > with a 64KB page size; then it is possible to use 52-bits of address > space for both userspace and kernel addresses. However, any kernel > binary that supports 52-bit must also be able to fall back to 48-bit > at early boot time if the hardware feature is not present. > > Since TCR_EL1.T1SZ indicates the size offset of the memory region > addressed by TTBR1_EL1 (and hence can be used for determining the > vabits_actual value) it makes more sense to export the same in > vmcoreinfo rather than vabits_actual variable, as the name of the > variable can change in future kernel versions, but the architectural > constructs like TCR_EL1.T1SZ can be used better to indicate intended > specific fields to user-space. > > User-space utilities like makedumpfile and crash-utility, need to > read this value from vmcoreinfo for determining if a virtual > address lies in the linear map range. > > While at it also add documentation for TCR_EL1.T1SZ variable being > added to vmcoreinfo. > > It indicates the size offset of the memory region addressed by TTBR1_EL1 > > Cc: James Morse > Cc: Mark Rutland > Cc: Will Deacon > Cc: Steve Capper > Cc: Catalin Marinas > Cc: Ard Biesheuvel > Cc: Dave Anderson > Cc: Kazuhito Hagio > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: kexec@lists.infradead.org > Tested-by: John Donnelly > Signed-off-by: Bhupesh Sharma I tested this for both 48 and 52 VA. The dump log looks fine with the crash tool link provided by you so, Tested-by: Amit Daniel Kachhap Also the code changes/documentation looks fine to me with a minor comments below, Reviewed-by: Amit Daniel Kachhap > --- > Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ > arch/arm64/include/asm/pgtable-hwdef.h | 1 + > arch/arm64/kernel/crash_core.c | 10 ++++++++++ > 3 files changed, 22 insertions(+) > > diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst > index 2a632020f809..2baad0bfb09d 100644 > --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst > +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst > @@ -404,6 +404,17 @@ KERNELPACMASK > The mask to extract the Pointer Authentication Code from a kernel virtual > address. > > +TCR_EL1.T1SZ > +------------ > + > +Indicates the size offset of the memory region addressed by TTBR1_EL1. > +The region size is 2^(64-T1SZ) bytes. > + > +TTBR1_EL1 is the table base address register specified by ARMv8-A > +architecture which is used to lookup the page-tables for the Virtual > +addresses in the higher VA range (refer to ARMv8 ARM document for > +more details). > + > arm > === > > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index 6bf5e650da78..a1861af97ac9 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -216,6 +216,7 @@ > #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) > #define TCR_TxSZ_WIDTH 6 > #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) > +#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET) > > #define TCR_EPD0_SHIFT 7 > #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) > diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c > index 1f646b07e3e9..314391a156ee 100644 > --- a/arch/arm64/kernel/crash_core.c > +++ b/arch/arm64/kernel/crash_core.c > @@ -7,6 +7,14 @@ > #include > #include > #include > +#include Nit: May be you forgot to include here as suggested by James in v5. Cheers, Amit > + > +static inline u64 get_tcr_el1_t1sz(void); > + > +static inline u64 get_tcr_el1_t1sz(void) > +{ > + return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; > +} > > void arch_crash_save_vmcoreinfo(void) > { > @@ -16,6 +24,8 @@ void arch_crash_save_vmcoreinfo(void) > kimage_voffset); > vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n", > PHYS_OFFSET); > + vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n", > + get_tcr_el1_t1sz()); > vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset()); > vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n", > system_supports_address_auth() ? > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F619C433E0 for ; Wed, 1 Jul 2020 08:05:48 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D8F020775 for ; Wed, 1 Jul 2020 08:05:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="iCiHEzTm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D8F020775 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fyvJRa4rLeAjJU5gVACTj+WjNPsWrUQKeaRbyeJI3qo=; b=iCiHEzTmSLcwSfGVqPGbuXE2R kgVz7bTM2dtcXudVr8J3IrkBYP68BOP4/z8Ecae3vyci8hIUU/mq//Ji7A/7piumc3P4M5/4VxvF8 2t7jflfJf0IyQfxYrEtug0uVSac+3a7Wz40k22U9Ci3HK1GPWrSOeUEvZRVSZ3eB8MNibM3iLKz7O sot2N+U1HCKs4Dypp9ZpVBTRKa44oO9EF4PiulrOVSpKvFiilpOhR4oCYL2HXhK1CJRy8UZTHNnfN 2ZCWrQ/oNDZgWGqDE7ZtpawAwqJlkh+q9gus1ACRUslihzYHkP6ESOUGTfA3QennjiLOXow4w9tZn 5fydeCD2Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqXj3-0005tW-2W; Wed, 01 Jul 2020 08:04:13 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqXiz-0005s6-IW; Wed, 01 Jul 2020 08:04:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62B9B31B; Wed, 1 Jul 2020 01:04:07 -0700 (PDT) Received: from [10.57.4.20] (unknown [10.57.4.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B2AD43F68F; Wed, 1 Jul 2020 01:04:03 -0700 (PDT) Subject: Re: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo To: Bhupesh Sharma , linux-arm-kernel@lists.infradead.org, x86@kernel.org References: <1589395957-24628-1-git-send-email-bhsharma@redhat.com> <1589395957-24628-3-git-send-email-bhsharma@redhat.com> From: Amit Kachhap Message-ID: <9b44a21d-93e0-8e5d-019c-fd360bf0504b@arm.com> Date: Wed, 1 Jul 2020 13:34:00 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <1589395957-24628-3-git-send-email-bhsharma@redhat.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200701_040409_714611_9D7E4ABF X-CRM114-Status: GOOD ( 32.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Kazuhito Hagio , Ard Biesheuvel , Catalin Marinas , Steve Capper , kexec@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse , Dave Anderson , bhupesh.linux@gmail.com, Will Deacon Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Bhupesh, On 5/14/20 12:22 AM, Bhupesh Sharma wrote: > vabits_actual variable on arm64 indicates the actual VA space size, > and allows a single binary to support both 48-bit and 52-bit VA > spaces. > > If the ARMv8.2-LVA optional feature is present, and we are running > with a 64KB page size; then it is possible to use 52-bits of address > space for both userspace and kernel addresses. However, any kernel > binary that supports 52-bit must also be able to fall back to 48-bit > at early boot time if the hardware feature is not present. > > Since TCR_EL1.T1SZ indicates the size offset of the memory region > addressed by TTBR1_EL1 (and hence can be used for determining the > vabits_actual value) it makes more sense to export the same in > vmcoreinfo rather than vabits_actual variable, as the name of the > variable can change in future kernel versions, but the architectural > constructs like TCR_EL1.T1SZ can be used better to indicate intended > specific fields to user-space. > > User-space utilities like makedumpfile and crash-utility, need to > read this value from vmcoreinfo for determining if a virtual > address lies in the linear map range. > > While at it also add documentation for TCR_EL1.T1SZ variable being > added to vmcoreinfo. > > It indicates the size offset of the memory region addressed by TTBR1_EL1 > > Cc: James Morse > Cc: Mark Rutland > Cc: Will Deacon > Cc: Steve Capper > Cc: Catalin Marinas > Cc: Ard Biesheuvel > Cc: Dave Anderson > Cc: Kazuhito Hagio > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: kexec@lists.infradead.org > Tested-by: John Donnelly > Signed-off-by: Bhupesh Sharma I tested this for both 48 and 52 VA. The dump log looks fine with the crash tool link provided by you so, Tested-by: Amit Daniel Kachhap Also the code changes/documentation looks fine to me with a minor comments below, Reviewed-by: Amit Daniel Kachhap > --- > Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ > arch/arm64/include/asm/pgtable-hwdef.h | 1 + > arch/arm64/kernel/crash_core.c | 10 ++++++++++ > 3 files changed, 22 insertions(+) > > diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst > index 2a632020f809..2baad0bfb09d 100644 > --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst > +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst > @@ -404,6 +404,17 @@ KERNELPACMASK > The mask to extract the Pointer Authentication Code from a kernel virtual > address. > > +TCR_EL1.T1SZ > +------------ > + > +Indicates the size offset of the memory region addressed by TTBR1_EL1. > +The region size is 2^(64-T1SZ) bytes. > + > +TTBR1_EL1 is the table base address register specified by ARMv8-A > +architecture which is used to lookup the page-tables for the Virtual > +addresses in the higher VA range (refer to ARMv8 ARM document for > +more details). > + > arm > === > > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index 6bf5e650da78..a1861af97ac9 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -216,6 +216,7 @@ > #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) > #define TCR_TxSZ_WIDTH 6 > #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) > +#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET) > > #define TCR_EPD0_SHIFT 7 > #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) > diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c > index 1f646b07e3e9..314391a156ee 100644 > --- a/arch/arm64/kernel/crash_core.c > +++ b/arch/arm64/kernel/crash_core.c > @@ -7,6 +7,14 @@ > #include > #include > #include > +#include Nit: May be you forgot to include here as suggested by James in v5. Cheers, Amit > + > +static inline u64 get_tcr_el1_t1sz(void); > + > +static inline u64 get_tcr_el1_t1sz(void) > +{ > + return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; > +} > > void arch_crash_save_vmcoreinfo(void) > { > @@ -16,6 +24,8 @@ void arch_crash_save_vmcoreinfo(void) > kimage_voffset); > vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n", > PHYS_OFFSET); > + vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n", > + get_tcr_el1_t1sz()); > vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset()); > vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n", > system_supports_address_auth() ? > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Subject: Re: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo References: <1589395957-24628-1-git-send-email-bhsharma@redhat.com> <1589395957-24628-3-git-send-email-bhsharma@redhat.com> From: Amit Kachhap Message-ID: <9b44a21d-93e0-8e5d-019c-fd360bf0504b@arm.com> Date: Wed, 1 Jul 2020 13:34:00 +0530 MIME-Version: 1.0 In-Reply-To: <1589395957-24628-3-git-send-email-bhsharma@redhat.com> Content-Language: en-US List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "kexec" Errors-To: kexec-bounces+dwmw2=infradead.org@lists.infradead.org To: Bhupesh Sharma , linux-arm-kernel@lists.infradead.org, x86@kernel.org Cc: Mark Rutland , Kazuhito Hagio , Ard Biesheuvel , Catalin Marinas , Steve Capper , kexec@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse , Dave Anderson , bhupesh.linux@gmail.com, Will Deacon Hi Bhupesh, On 5/14/20 12:22 AM, Bhupesh Sharma wrote: > vabits_actual variable on arm64 indicates the actual VA space size, > and allows a single binary to support both 48-bit and 52-bit VA > spaces. > > If the ARMv8.2-LVA optional feature is present, and we are running > with a 64KB page size; then it is possible to use 52-bits of address > space for both userspace and kernel addresses. However, any kernel > binary that supports 52-bit must also be able to fall back to 48-bit > at early boot time if the hardware feature is not present. > > Since TCR_EL1.T1SZ indicates the size offset of the memory region > addressed by TTBR1_EL1 (and hence can be used for determining the > vabits_actual value) it makes more sense to export the same in > vmcoreinfo rather than vabits_actual variable, as the name of the > variable can change in future kernel versions, but the architectural > constructs like TCR_EL1.T1SZ can be used better to indicate intended > specific fields to user-space. > > User-space utilities like makedumpfile and crash-utility, need to > read this value from vmcoreinfo for determining if a virtual > address lies in the linear map range. > > While at it also add documentation for TCR_EL1.T1SZ variable being > added to vmcoreinfo. > > It indicates the size offset of the memory region addressed by TTBR1_EL1 > > Cc: James Morse > Cc: Mark Rutland > Cc: Will Deacon > Cc: Steve Capper > Cc: Catalin Marinas > Cc: Ard Biesheuvel > Cc: Dave Anderson > Cc: Kazuhito Hagio > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: kexec@lists.infradead.org > Tested-by: John Donnelly > Signed-off-by: Bhupesh Sharma I tested this for both 48 and 52 VA. The dump log looks fine with the crash tool link provided by you so, Tested-by: Amit Daniel Kachhap Also the code changes/documentation looks fine to me with a minor comments below, Reviewed-by: Amit Daniel Kachhap > --- > Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ > arch/arm64/include/asm/pgtable-hwdef.h | 1 + > arch/arm64/kernel/crash_core.c | 10 ++++++++++ > 3 files changed, 22 insertions(+) > > diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst b/Documentation/admin-guide/kdump/vmcoreinfo.rst > index 2a632020f809..2baad0bfb09d 100644 > --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst > +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst > @@ -404,6 +404,17 @@ KERNELPACMASK > The mask to extract the Pointer Authentication Code from a kernel virtual > address. > > +TCR_EL1.T1SZ > +------------ > + > +Indicates the size offset of the memory region addressed by TTBR1_EL1. > +The region size is 2^(64-T1SZ) bytes. > + > +TTBR1_EL1 is the table base address register specified by ARMv8-A > +architecture which is used to lookup the page-tables for the Virtual > +addresses in the higher VA range (refer to ARMv8 ARM document for > +more details). > + > arm > === > > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index 6bf5e650da78..a1861af97ac9 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -216,6 +216,7 @@ > #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) > #define TCR_TxSZ_WIDTH 6 > #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET) > +#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET) > > #define TCR_EPD0_SHIFT 7 > #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) > diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c > index 1f646b07e3e9..314391a156ee 100644 > --- a/arch/arm64/kernel/crash_core.c > +++ b/arch/arm64/kernel/crash_core.c > @@ -7,6 +7,14 @@ > #include > #include > #include > +#include Nit: May be you forgot to include here as suggested by James in v5. Cheers, Amit > + > +static inline u64 get_tcr_el1_t1sz(void); > + > +static inline u64 get_tcr_el1_t1sz(void) > +{ > + return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; > +} > > void arch_crash_save_vmcoreinfo(void) > { > @@ -16,6 +24,8 @@ void arch_crash_save_vmcoreinfo(void) > kimage_voffset); > vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n", > PHYS_OFFSET); > + vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n", > + get_tcr_el1_t1sz()); > vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset()); > vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n", > system_supports_address_auth() ? > _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec