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Sun, 19 Sep 2021 11:33:00 -0700 (PDT) Received: from [192.168.1.11] ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id f144sm11853116pfa.24.2021.09.19.11.32.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 19 Sep 2021 11:32:59 -0700 (PDT) Subject: Re: [PATCH v2 19/41] hw/core: Add TCGCPUOps.record_sigsegv To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org References: <20210918184527.408540-1-richard.henderson@linaro.org> <20210918184527.408540-20-richard.henderson@linaro.org> <95b28dff-7a3c-73fa-2449-c41110e12642@amsat.org> From: Richard Henderson Message-ID: <9b6c37ea-2a14-882b-a770-0cefddeba218@linaro.org> Date: Sun, 19 Sep 2021 11:32:58 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/19/21 11:24 AM, Philippe Mathieu-Daudé wrote: > On 9/19/21 20:22, Philippe Mathieu-Daudé wrote: >> On 9/18/21 20:45, Richard Henderson wrote: >>> Add a new user-only interface for updating cpu state before >>> raising a signal. This will replace tlb_fill for user-only >>> and should result in less boilerplate for each guest. >>> >>> Signed-off-by: Richard Henderson >>> --- >>> include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ >>> 1 file changed, 26 insertions(+) >>> >>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h >>> index 4a4c4053e3..e229a40772 100644 >>> --- a/include/hw/core/tcg-cpu-ops.h >>> +++ b/include/hw/core/tcg-cpu-ops.h >>> @@ -114,6 +114,32 @@ struct TCGCPUOps { >>> */ >>> bool (*io_recompile_replay_branch)(CPUState *cpu, >>> const TranslationBlock *tb); >>> +#else >>> + /** >>> + * record_sigsegv: >>> + * @cpu: cpu context >>> + * @addr: faulting guest address >>> + * @access_type: access was read/write/execute >>> + * @maperr: true for invalid page, false for permission fault >>> + * @ra: host pc for unwinding >>> + * >>> + * We are about to raise SIGSEGV with si_code set for @maperr, >>> + * and si_addr set for @addr. Record anything further needed >>> + * for the signal ucontext_t. >>> + * >>> + * If the emulated kernel does not provide anything to the signal >>> + * handler with anything besides the user context registers, and >>> + * the siginfo_t, then this hook need do nothing and may be omitted. >>> + * Otherwise, record the data and return; the caller will raise >>> + * the signal, unwind the cpu state, and return to the main loop. >>> + * >>> + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided >>> + * so that a "normal" cpu exception can be raised. In this case, >>> + * the signal must be raised by the architecture cpu_loop. >>> + */ >> >> Shouldn't it have the QEMU_NORETURN attribute? > > Eh now I saw the next patch and understood raise_sigsegv() is > where QEMU_NORETURN belong :) Well, I had intended the hook to be able to return, so that the hook can merely set some env->fields, and return to raise the signal. But in the end, all 4 targets that use the hook raise the exception themselves -- sometimes because env->exception_index is part of the data to be passed to the signal handler. r~