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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver
Date: Mon, 5 Oct 2009 16:29:06 +0800	[thread overview]
Message-ID: <9bf601f70910050129h2996e169lbc514e4950bd968d@mail.gmail.com> (raw)
In-Reply-To: <F2F605B667B24B489C904986E0D60A08FF6226@zin33exm23.fsl.freescale.net>

Hi Dipen,

On Thu, Oct 1, 2009 at 12:48 PM, Dudhat Dipen-B09055
<Dipen.Dudhat@freescale.com> wrote:
>
> Hi Bin,
>
> We can know the block transfer complete using IRQSTAT(Transfer
> Complete).
> But reading & writing in PIO mode takes time for byte by byte transfers
> and there is no way to poll that transfer, that's why I have added delay
> there.
>

Yes, I understand there is no such a register in Freescale eSDHC that
provides status check for PIO mode.
I am just wondering where the delay value 100 us comes from. Is it the
required minimum value?

> I can add comment like,
> \* Wait before last byte transfer complete *\
> Is that ok ??
>

Sure, adding a comment line would help a lot.

Regards,
Bin Meng

  reply	other threads:[~2009-10-05  8:29 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-09-10 13:37 [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver Dipen Dudhat
2009-09-22 18:41 ` Wolfgang Denk
2009-09-23  7:38   ` Dudhat Dipen-B09055
2009-09-27 23:11 ` Bin Meng
2009-10-01  4:48   ` Dudhat Dipen-B09055
2009-10-05  8:29     ` Bin Meng [this message]
2009-10-05  8:38       ` Dudhat Dipen-B09055
2009-09-14  4:56 Dipen Dudhat
2009-09-22 20:17 ` Wolfgang Denk

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