Re: [PATCH 11/11] arm64: dts: Add Pensando Elba SoC support

From: Marc Zyngier <maz@kernel.org>
To: Brad Larson <brad@pensando.io>
Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de,
	linus.walleij@linaro.org, bgolaszewski@baylibre.com,
	broonie@kernel.org, fancer.lancer@gmail.com,
	adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net,
	dac2@pensando.io, linux-gpio@vger.kernel.org,
	linux-spi@vger.kernel.org, linux-mmc@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 11/11] arm64: dts: Add Pensando Elba SoC support
Date: Thu, 07 Apr 2022 08:57:44 +0100	[thread overview]
Message-ID: <9c08f621be28dba65e811bc9cdedc882@kernel.org> (raw)
In-Reply-To: <20220406233648.21644-12-brad@pensando.io>

On 2022-04-07 00:36, Brad Larson wrote:
> Add Pensando common and Elba SoC specific device nodes
> 
> Signed-off-by: Brad Larson <brad@pensando.io>
> ---
> Change from V3:
> - Changed to dual copyright (GPL-2.0+ OR MIT)
> - Minor changes from review input
> 
>  arch/arm64/boot/dts/Makefile                  |   1 +
>  arch/arm64/boot/dts/pensando/Makefile         |   3 +
>  arch/arm64/boot/dts/pensando/elba-16core.dtsi | 189 ++++++++++++++++++
>  .../boot/dts/pensando/elba-asic-common.dtsi   |  98 +++++++++
>  arch/arm64/boot/dts/pensando/elba-asic.dts    |  28 +++
>  .../boot/dts/pensando/elba-flash-parts.dtsi   | 106 ++++++++++
>  arch/arm64/boot/dts/pensando/elba.dtsi        | 189 ++++++++++++++++++
>  7 files changed, 614 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/pensando/Makefile
>  create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
>  create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
>  create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
>  create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
>  create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi
> 

[...]

> diff --git a/arch/arm64/boot/dts/pensando/elba.dtsi
> b/arch/arm64/boot/dts/pensando/elba.dtsi
> new file mode 100644
> index 000000000000..10e06eb8cda6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba.dtsi

[...]

> +		gic: interrupt-controller@800000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <3>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			interrupt-controller;
> +			reg = <0x0 0x800000 0x0 0x200000>,	/* GICD */
> +			      <0x0 0xa00000 0x0 0x200000>;	/* GICR */

You are still missing the GICV and GICH regions that are
provided by the CPU. I already pointed that out in [1].

The Cortex-A72 TRM will tell you where to find them (at
an offset from PERIPHBASE).

Please fix this.

         M.

[1] 
https://lore.kernel.org/all/a20805de16e1196c2ed46dd949473c9a@kernel.org
-- 
Jazz is not dead. It just smells funny...