From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752009AbeE0WLV (ORCPT ); Sun, 27 May 2018 18:11:21 -0400 Received: from mail-ve1eur01on0108.outbound.protection.outlook.com ([104.47.1.108]:26304 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751532AbeE0WLQ (ORCPT ); Sun, 27 May 2018 18:11:16 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=peda@axentia.se; Subject: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma From: Peter Rosin To: Tudor Ambarus , Nicolas Ferre , Ludovic Desroches Cc: Alexandre Belloni , Marek Vasut , Josh Wu , Cyrille Pitchen , linux-kernel@vger.kernel.org, Boris Brezillon , linux-mtd@lists.infradead.org, Richard Weinberger , Brian Norris , David Woodhouse , linux-arm-kernel@lists.infradead.org, Eugen Hristev References: <20180329131054.22506-1-peda@axentia.se> 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=?utf-8?B?Rk9rR2c5RVZ5TE1Ybk1TKzBnUUNNV3M5T3RCR3pacTcrdHdVMEdCajlDaUlk?= =?utf-8?B?OHpieUhBaGRUVFQzZndGMUU3Wmp2NGVabGNjVlNFT1F4RmM1UVJWNElFVWFn?= =?utf-8?B?UGRkQldlakR5a0Ric1RxNkExaGJUSVkyS3EybTdodW85VFlkQSttQ2U5RldZ?= =?utf-8?B?aFJGZlRyVlBUWFR2cXhodWxLUXVqTlJ0N2l2SGdKN1hwUHA1QzZKK1hmRmJR?= =?utf-8?B?eC9vNDQzZmdXTis4UXBTNFBkRStobkJEM3NzNFBzVmg1Ry8zQnl2MnAzanVr?= =?utf-8?B?NkV4NGpwbWJyYytqNnpMVWlNalRza2t3MGs4VWhPemNod1NYV2dtKzBLdjB4?= =?utf-8?B?SjN6VmVmenVUMkt5bzlVVHNLTHFuUURmM1o0LzZEbEtrSVlhQXVncHFiMGNR?= =?utf-8?B?czlGSTQ1ME81U25MT0QxdVZySUdwOW1mUTUvMTNTcFRxMVErQ0NoK0J3ZmN3?= =?utf-8?B?dEwvZllsa0g0NmtMaFdaVkZrSU9RaFpPZTdFYXkydjJqcnJvL1ZIdG1zWU1p?= =?utf-8?B?cy9vTUhCTDZSRmZuaG9ObmFzZU1OaGY3YWlwakJLWExXTkc3WEpRU1JaVnFp?= =?utf-8?B?TXlGUno5Y0MrcTE3b21JZWpiWUE0TTlrOTdUTXJRNVkrZFdiWTJtd1RudEp0?= =?utf-8?B?US82SFdKcG1PU1FlRWFPL2UzZ1dPLzY2MXBxSnBwanVhcEZGRzczVFNFQ2tw?= =?utf-8?B?VWUzQnBDZkpqVXdZYkpSWWtnTkFHMEJhQnVBRWYxaFlnR3JFdXMzbmdBbGpG?= =?utf-8?B?cTU0QUw3STYzTGxtUlFobWFVdEJrbmRCYktwaW9LK2VQdUw4WU9QODdEdEFh?= =?utf-8?B?RllvNHM0N1ZHSWU3MEIyemU1aDhORlZ4MVlEcjFTQnhPOTYzcUNBUUFjUWg1?= =?utf-8?B?NEJnZ1V6dnlVL0gwWW13dzdqTWtMMUlQdE03aVRWUGhndEFLbk52K091Q2FE?= =?utf-8?B?NDVrM0szZi9VSFlCWW41Rnc1bzZVQmRQZXRSUGNVRzFUbEFWdmxtcGtsVFh0?= =?utf-8?B?TWpYL1VDRkxSOS9jdkRrSCtWMEExbW1MZ283RXkyYkYwb2V2UVJuTHl0NlVp?= =?utf-8?B?d0Z6YzRzK20yYTByK3p4N21YZmdXMkV3TkhlYUNFSGpUWWhiMkF0S1hibFJ1?= =?utf-8?B?YmlENSsrNHAxc2c5TjhScjFpbG9pSnJueXZZUEhVVjNYcUlac0hwTnZCdS8y?= =?utf-8?B?eDNDZ0FmK2J1cVF0UDF5MHJWcm9UYmVpOGtJNXFRS0s1RVAydG8zdUl5MHdE?= =?utf-8?B?SmFLZFRSUWlwQ004MmgyRnZ2L3k3b3B4eGJVNng1aXRHaStPQ0tZaitJbEZy?= =?utf-8?B?RjVsNW5zTWU5Zm44WGhuOUZ5MElwN20xNVRxTFRjdWNIc2JTZnlOa0w2UGpG?= =?utf-8?B?eG9zZFlHZHMyRnhaaTkvMzA4M3pRR0VPb1pMZjVwM0NLVk1yaDljUDNQSzNI?= =?utf-8?B?VTR5UHROUnhNcUJJa1hRTEU4dTYvWllYNkovYTEyWWpmODVTOG03VzhiYjYw?= =?utf-8?B?Q1krcW85Ums5a3BkV1dEQmJReVJGTFZhL1RlZXJjL1dySUJPTDliOU9YSytE?= =?utf-8?B?cXNHblJSeTExOUEyRDNmek9zWG83ZmlvM0FoZHhDTWFJMTZRNWZzazlSVmYz?= =?utf-8?B?bS8vNWl4TjRvMEtwU1laMmRCdTFyamFyK213eU9RNEkyWmxDZThxWTJzYlp3?= =?utf-8?B?dHRsekZneWxpOC9CaTFKUkxaZXFMVnpaSFNURlpNaUdhOXBMRDJ2MENTK0Nx?= =?utf-8?B?enN3Rk03MUV3R0QwT2psNzBqSENndnYxemE0bGpXV1lreVBPOEFRNUZhL3B2?= =?utf-8?B?SkNNS0xWMEZlTVk5S1JJQ1hYUm5Kekd1MUJnY2creUJwV2dPbXFIQkptQm0w?= =?utf-8?B?SUF0bXAzK0J6TEh1MDNLZVhDK0RrNytBRkxYRXBJVDhRUVFIWE1pbVptdGla?= =?utf-8?B?R2swVkxVa2xFdWdBVHM4UHM0TTN4VThZalRQb0xCaUc2UGM3alpvUGRBa1Iy?= =?utf-8?B?MHp0c3MzOThlRnlHSDNRYkEvUWZOdEZPTW5EVDYySHVSeUluQVNDV2FMQS81?= =?utf-8?B?MHVhREJBcGZpam5FRXB0U3d0WCszTG5Rc1JnWGszdGU1UXcweUlzMUNpUHc2?= =?utf-8?B?QjBYRVllakw3aW9HemNNRys0NmxDR1FISUpvd0ExaGhuZ2hCNEQyWUs3OFo0?= =?utf-8?B?VmIzNGtxOURrcTN2Vk1BT2lKa0VublpNSUNjUTFWRjFkT1ZHNW41Y0xRPT0=?= X-Microsoft-Antispam-Message-Info: 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1;DB6PR0201MB2455;7:z+tAAvsdO075RQjJue4nJSng3H4A6guFhmCzvQwzS3CO1oB0hYy0N74qXQgar2zxGl8grOkOuW61hbQdg+FYeiEFH1aL/8BkyhJ0jdi6eDG3RV/BZSsV2G2czRFwU5zoVlx78IjTts9J0Q4kb8I6IqdU+k9Swc8Eio6D7Jo0cd/I279roxoDVYihOQF69d1ixlr54iXNk5ijEfLapWIRDUOJF/+5wmqt7nYgqpY0tl/sEDQ0XSW88LhuINpIpPnD X-MS-Office365-Filtering-Correlation-Id: 03746d00-3dcb-4b5d-3b16-08d5c41ec22a X-OriginatorOrg: axentia.se X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 May 2018 22:11:11.6393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03746d00-3dcb-4b5d-3b16-08d5c41ec22a X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4ee68585-03e1-4785-942a-df9c1871a234 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0201MB2455 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2018-05-27 11:18, Peter Rosin wrote: > On 2018-05-25 16:51, Tudor Ambarus wrote: >> We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th >> slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND >> (7th slave). > > Exactly how do I accomplish that? > > I can see how I can move the LCD between slave DDR port 2 and 3 by > selecting LCDC DMA master 8 or 9 (but according to the above it should > not matter). The big question is how I control what slave the NAND flash > is going to use? I find nothing in the datasheet, and the code is also > non-transparent enough for me to figure it out by myself without > throwing out this question first... I added this: diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index e686fe73159e..3b33c63d2ed4 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1991,6 +1991,9 @@ static int atmel_nand_controller_init(struct atmel_nand_controller *nc, nc->dmac = dma_request_channel(mask, NULL, NULL); if (!nc->dmac) dev_err(nc->dev, "Failed to request DMA channel\n"); + + dev_info(nc->dev, "using %s for DMA transfers\n", + dma_chan_name(nc->dmac)); } /* We do not retrieve the SMC syscon when parsing old DTs. */ and the output is atmel-nand-controller 10000000.ebi:nand-controller: using dma0chan5 for DMA transfers So, DMA controller 0 is in use. I still don't know if IF0, IF1 or IF2 is used or how to find out. I guess IF2 is not in use since that does not allow any DDR2 port as slave... >>From the datasheet, DMAC0/IF0 uses DDR2 Port 2, and DMAC0/IF1 uses DDR2 Port 1. But, by the looks of the register content in my other mail, it seems as if DMA0/IF1 can also use DDR2 Port 3. So, I think I want either A) the NAND controller to use DMAC0/IF0 (i.e. DDR2 port 1, and possibly 3) and the LCDC to use master 9 (i.e. DDR2 Port 2) or B) the NAND controller to use DMAC1/IF1 (i.e. DDR2 port 2) and the LCDC to use master 8 (i.e. DDR2 Port 3) But, again, how do I limit DMAC0 to either of IF0 or IF1 for NAND accesses? Note that I have previously tried to move LCDC DMA from master 8 (the default) to master 9, and it got better, but not good enough. I.e. the visual glitches remained, but were a little bit harder to trigger. That makes me suspect DMAC0 uses both IF0 and IF1 for its DMAs, but that it prefers IF0. Cheers, Peter From mboxrd@z Thu Jan 1 00:00:00 1970 From: peda@axentia.se (Peter Rosin) Date: Mon, 28 May 2018 00:11:07 +0200 Subject: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma In-Reply-To: <024079cb-77ad-9c48-e370-e6e8f2de171b@axentia.se> References: <20180329131054.22506-1-peda@axentia.se> <20180329153322.5e2fc1e7@bbrezillon> <20180329154416.5c1a0013@bbrezillon> <20180402142249.7e076a64@bbrezillon> <20180402212843.164d5d21@bbrezillon> <20180402222020.1d344c14@bbrezillon> <20180403091813.5fb5c18c@bbrezillon> <959d826d-1a98-ca22-acee-a4548427fcd3@microchip.com> <024079cb-77ad-9c48-e370-e6e8f2de171b@axentia.se> Message-ID: <9c496531-f7b6-4b9d-dd51-0bfb68ead303@axentia.se> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 2018-05-27 11:18, Peter Rosin wrote: > On 2018-05-25 16:51, Tudor Ambarus wrote: >> We think the best way is to keep LCD on DDR Ports 2 and 3 (8th and 9th >> slaves), to have maximum bandwidth and to use DMA on DDR port 1 for NAND >> (7th slave). > > Exactly how do I accomplish that? > > I can see how I can move the LCD between slave DDR port 2 and 3 by > selecting LCDC DMA master 8 or 9 (but according to the above it should > not matter). The big question is how I control what slave the NAND flash > is going to use? I find nothing in the datasheet, and the code is also > non-transparent enough for me to figure it out by myself without > throwing out this question first... I added this: diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index e686fe73159e..3b33c63d2ed4 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1991,6 +1991,9 @@ static int atmel_nand_controller_init(struct atmel_nand_controller *nc, nc->dmac = dma_request_channel(mask, NULL, NULL); if (!nc->dmac) dev_err(nc->dev, "Failed to request DMA channel\n"); + + dev_info(nc->dev, "using %s for DMA transfers\n", + dma_chan_name(nc->dmac)); } /* We do not retrieve the SMC syscon when parsing old DTs. */ and the output is atmel-nand-controller 10000000.ebi:nand-controller: using dma0chan5 for DMA transfers So, DMA controller 0 is in use. I still don't know if IF0, IF1 or IF2 is used or how to find out. I guess IF2 is not in use since that does not allow any DDR2 port as slave... >>From the datasheet, DMAC0/IF0 uses DDR2 Port 2, and DMAC0/IF1 uses DDR2 Port 1. But, by the looks of the register content in my other mail, it seems as if DMA0/IF1 can also use DDR2 Port 3. So, I think I want either A) the NAND controller to use DMAC0/IF0 (i.e. DDR2 port 1, and possibly 3) and the LCDC to use master 9 (i.e. DDR2 Port 2) or B) the NAND controller to use DMAC1/IF1 (i.e. DDR2 port 2) and the LCDC to use master 8 (i.e. DDR2 Port 3) But, again, how do I limit DMAC0 to either of IF0 or IF1 for NAND accesses? Note that I have previously tried to move LCDC DMA from master 8 (the default) to master 9, and it got better, but not good enough. I.e. the visual glitches remained, but were a little bit harder to trigger. That makes me suspect DMAC0 uses both IF0 and IF1 for its DMAs, but that it prefers IF0. Cheers, Peter